Semiconductor Wafer Fabrication Facilities Research Articles

Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities

In semiconductor wafer fabrication facilities, order-lot pegging is the process of assigning wafer lots to orders and meeting the due dates of orders is considered one of the most important operational issues. In many cases of order-lot pegging, some orders cannot be fulfilled with the current wafers in the lots being processed, necessitating the release of additional new wafer lots into the wafer fabrication facility. In this paper, we propose a simultaneous decision model for order-lot pegging and wafer release planning in semiconductor wafer fabrication facilities, and develop a Lagrangian heuristic for solving the model. The results of computational experiments conducted using randomly generated problem instances that mimic actual field data from a Korea semiconductor wafer fabrication facility indicate that the performance of the Lagrangian heuristic is superior to that of a practical greedy algorithm for practical-sized problem instances. The results also point to how sensitivity analysis can be used to answer important managerial questions for effective management of the semiconductor wafer fabrication process.

Planning Wafer Starts Using Nonlinear Clearing Functions: A Large-Scale Experiment

The nonlinear, circular dependency between workload and cycle times for production resources governed by queueing behavior has been a longstanding difficulty in the production planning domain. The issue is particularly important for semiconductor wafer fabrication facilities, which must operate at relatively high utilization to be profitable. Nonlinear clearing functions that relate the expected output of a resource in a planning period to the amount of work available to it have been proposed as an alternative approach. While computational tests on small systems have been promising, the question of whether the results remain valid for large-scale systems has remained open. In this paper we evaluate the performance of a clearing function based production planning model using a simulation of a large-scale wafer fab with two products and several hundred operations. Results indicate that, consistent with the results of previous experiments, the clearing function model yields substantial improvements in profit over conventional linear programming models.

Adaptive Dispatching Rule for Semiconductor Wafer Fabrication Facility

Uncertainty in semiconductor fabrication facilities (fabs) requires scheduling methods to attain quick real-time responses. They should be well tuned to track the changes of a production environment to obtain better operational performance. This paper presents an adaptive dispatching rule (ADR) whose parameters are determined dynamically by real-time information relevant to scheduling. First, we introduce the workflow of ADR that considers both batch and non-batch processing machines to obtain improved fab-wide performance. It makes use of such information as due date of a job, workload of a machine, and occupation time of a job on a machine. Then, we use a backward propagation neural network (BPNN) and a particle swarm optimization (PSO) algorithm to find the relations between weighting parameters and real-time state information to adapt these parameters dynamically to the environment. Finally, a real fab simulation model is used to demonstrate the proposed method. The simulation results show that ADR with constant weighting parameters outperforms the conventional dispatching rule on average; ADR with changing parameters tracking real-time production information over time is more robust than ADR with constant ones; and further improvements can be obtained by optimizing the weights and threshold values of BPNN with a PSO algorithm.

Heuristic scheduling policies for a semiconductor wafer fabrication facility: minimizing variation of cycle times

This paper presents heuristic scheduling policies for semiconductor wafer fabrication facilities. The proposed heuristic scheduling policies include the advanced operation due date (OPNDD) for a sequence control policy and the adaptive constant work-in-process (CONWIP) for an input release control policy. The objective of the proposed scheduling policies is to reduce the variation of cycle times in the wafer fab. The advanced OPNDD sets the higher priority to the front opening unified pod (FOUP) with the smallest operation due date that is computed using a generalized stochastic Petri net model, and at the same time regulates the queue lengths of the FOUPs in each stoker by preventing excessive queue lengths in bottleneck workstations. The adaptive CONWIP controls dynamically the input release time of FOUPs using the adaptive WIP level according to the current status of the wafer fab. The simulation experiments show that the proposed scheduling method is efficient in reducing the variation of cycle times.

An integrated scheduling and material-handling approach for complex job shops: a computational study

We suggest an extension of the shifting bottleneck heuristic for complex job shops that takes the operations of automated material-handling systems (AMHS) into account. The heuristic is used within a rolling horizon approach. The job-shop environment contains parallel batching machines, machines with sequence-dependent setup times, and re-entrant process flows. Jobs are transported by an AMHS. Semiconductor wafer fabrication facilities (wafer fabs) are typical examples for manufacturing systems with these characteristics. Our primary performance measure is total weighted tardiness (TWT). The shifting bottleneck heuristic (SBH) uses a disjunctive graph to decompose the overall scheduling problem into scheduling problems for single machine groups and for transport operations. The scheduling algorithms for these scheduling problems are called subproblem solution procedures (SSPs). We consider SSPs based on dispatching rules. In this paper, we are also interested in how much we can gain in terms of TWT if we apply more sophisticated SSPs for scheduling the transport operations. We suggest a Variable Neighbourhood Search (VNS) based SSP for this situation. We conduct simulation experiments in a dynamic job-shop environment in order to assess the performance of the suggested algorithms. The integrated SBH outperforms common dispatching rules in many situations. Using near to optimal SSPs leads to improved results compared with dispatching based SSPs for the transport operations.

Multiproduct Lot Merging–Splitting Algorithms for Semiconductor Wafer Fabrication

This paper focuses on a lot merging-splitting problem in a semiconductor wafer fabrication facility in which a relatively large number of wafer types are produced according to orders with different due dates. In the fab, two or more lots can be merged into a single lot if routes and all processing conditions of the lots are the same for a number of subsequent operations, and the merged lot is split into the original lots at the point where the routes or processing conditions become different. We suggest lot merging-splitting algorithms to reduce the total tardiness of the orders and the cycle times of the lots. The suggested algorithms are evaluated through a series of simulation experiments and the result shows that the algorithms work better than a method used in a real fab.

Multi-ant colony-based sequencing method for semiconductor wafer fabrication facilities with multi-bottleneck

In this paper, a multi-ant colony optimisation method is proposed to make a sequence plan for a semiconductor wafer fabrication facility (fab) with multi-bottleneck. Its main idea is to find a scheduling solution for each bottleneck of the fab with an ant colony optimisation (ACO) algorithm first, then synchronise these solutions to reunify a sequence plan for these bottlenecks satisfying job sequence constraints, and finally obtain the scheduling plans of non-bottlenecks of the fab subject to that of bottlenecks and job sequence constraints. The sequence plan of the whole fab is translated into the pheromones to guide ant colonies to make their next search processes. There are two kinds of ACO algorithms in the multi-ant colony optimisation method. One (ACO-1) is for common machines and the other (ACO-2) is for batch processing machines. The mini-fab model and a simplified model from a real wafer fab are used to verify and validate the proposed method. The simulation results show that the multi-ant colony optimisation method improves the total weighted tardiness of jobs and the utilities of the bottlenecks with better performances.

Optimising the location of crossovers in conveyor-based automated material handling systems in semiconductor wafer fabs

This research presents several heuristics to optimise the location of crossovers in a conveyor-based automated material handling system (AMHS) for a semiconductor wafer fabrication facility. The objective is to determine the location of crossovers that minimises the total cost of the expected work-in-process on the conveyor and the cost of installing and operating the AMHS with the crossovers. The proposed heuristics are integrated with a queuing-based analytical model incorporating practical hardware considerations of the AMHS, such as turntables and crossovers. To illustrate the proposed heuristics’ practical application they are applied to SEMATECH's virtual wafer fabrication facility. Experimental results demonstrate that under a wide variety of operating conditions and cost scenarios the local improvement heuristic is able to identify the optimal solution and outperform other commonly used heuristics for layout design such as genetic algorithms.

Estimating the sustainable capacity of semiconductor fab workstations

The cost of a semiconductor wafer fabrication facility (i.e. ‘fab’) may be as much as five or more billion US dollars. As such it is essential to determine the capacity (e.g. in terms of ‘wafer starts per week’) of such facilities. An accurate estimate of capacity – under real world conditions – is, however, difficult to achieve. Furthermore, the method for the computation of the capacity of a semiconductor fab is significantly different from that for the capacity of workstations in more conventional, less complex factories. This is due in part to the reentrant nature of the workstations (a.k.a. ‘toolsets’) that comprise a fab's production line as well as the ubiquitous employment of operation-to-machine dedications (a.k.a. layer-to-tool qualifications) – plus the need to consider multiple products employing, perhaps, a different sequence of processing steps. In this article, the matter of workstation capacity, in general, and semiconductor fabs, in particular, is examined. A means to quickly and effectively determine the maximum theoretical capacity of a workstation is developed and illustrated – followed by a way in which the more practical maximum sustainable capacity may be estimated.

Prioritising production and engineering lots in wafer fabrication facilities: a simulation study

Due to the high cost of equipment, most semiconductor wafer fabrication facilities process both regular production lots which are shipped to customers and engineering lots that support product and process development efforts. The different objectives of the engineering and production organisations render the problem of allocating equipment capacity between these different types of lots a difficult and often contentious problem. In this paper we explore the impacts of several different policies for allocating resources to production and engineering work on the shop floor using a scaled-down simulation model of a wafer fabrication facility. Our results indicate that the availability and flexibility of engineering resources can affect the performance of scheduling policies in quite different ways. We conclude that this problem needs to be viewed in a broader context than that of a shop floor scheduling issue, including the level of available engineering resources, their degree of cross-training and the manner in which engineers are allocated to different projects.

A Swarm Intelligence Based Rescheduling Method for Semiconductor Wafer Fabrication Facilities

An effective rescheduling method takes an important role on improving the operational performance of a semiconductor wafer fabrication facility (fabs). In this paper, we propose a rescheduling method based on swarm intelligence. Firstly, we build a swarm intelligence based rescheduling model (SIRM) including an ant queen agent, multiple job ant agents and machine ant agents. Secondly, we design a rescheduling algorithm (CMRA) composed of three sub-algorithms: sub-algorithm-1 is used by an ant queen agent to transfer an existing static optimized scheduling plan into additional pheromones of job ant agents; sub-algorithm-2 and sub-algorithm-3 are used to convert scheduling related real-time information to dynamic pheromones of job ant agents and machine ant agents, respectively. Finally, a simplified semiconductor wafer fab model is used to verify and validate CMRA. The simulation results demonstrate that CMRA is superior to the original scheduling method to generate a static optimized scheduling plan with better performance on move, step and on-time operational due date rate under uncertain production environments.

Multiple orders per job formation and release strategies in large-scale wafer fabs: a simulation study

In this paper, multiple orders per job type formation and release strategies are described for semiconductor wafer fabrication facilities (wafer fabs). Different orders are grouped into one job because orders of an individual customer very often fill only a portion of a Front-Opening Unified Pod (FOUP). After job formation, an FOUP is assigned to each job and is used to move the job throughout the wafer fab. We determine an acceptable number of FOUPs given a prescribed order release rate to find appropriate values for on-time delivery performance measures, cycle time, and throughput by discrete event simulation. On the other hand, given a prescribed number of FOUPs and target values for these performance measures, we look for an appropriate order release rate. Simulation experiments with models for large-scale wafer fabs are performed to solve these two problems. We also discuss a complementary analytical method to determine an appropriate number of FOUPs in some specific situations.

An Analytical Model for Conveyor-Based Material Handling System With Crossovers in Semiconductor Wafer Fabs

This paper proposes a queueing-based analytical model useful in the design of closed-loop conveyor-based automated material handling system (AMHS), which has been identified as an effective material handling alternative in next-generation semiconductor wafer fabrication facilities. The model presented in this paper represents practical hardware considerations of the AMHS, such as turntables and crossovers. The objective is to accurately estimate the expected work-in-process (WIP) on the conveyor, queueing delays due to congestion at intersection points, as well as assessing the conveyor system stability. A four-phase approach is used to estimate the WIP. The proposed model is applied to the SEMATECH virtual 300 mm wafer fab. Experimental results demonstrate that in the worst case where the maximum number of crossovers is used and the traffic on the conveyor is high, the analytical model performs very well with average relative errors of 4.2%.

Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility

This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice.

Hierarchical Production Planning for Semiconductor Wafer Fabrication Based on Linear Programming and Discrete-Event Simulation

This paper focuses on a production planning and scheduling problem in a semiconductor wafer fabrication facility. We propose a two-level hierarchical production planning (HPP) method that employs an itmmerative procedure for production planning and operations scheduling. In the method, production plans are obtained with a linear programming (LP) model in the aggregate level, and schedules at the machines are obtained with a priority-rule-based scheduling method and evaluated with discrete-event simulation in the disaggregate level. An iterative scheme is adopted for obtaining a good and feasible production plan. The proposed method is evaluated through simulation experiments and the results show that the method works better than an existing algorithm in terms of the total production cost and total tardiness of orders.

Cycle time reduction via machine-to-operation qualification

In the utopian factory every machine in a workstation would be qualified to perform every operation supported by that workstation (e.g., able to run every associated photolithography layer of the semiconductor wafer fabrication process). In real world factories this is unlikely to be either practical or even feasible. As a consequence, one of the more vexing problems involved in determination of factory configuration and operation is that of deciding which operations are to be run on what machine, so as to optimise overall factory performance. In this paper the decision of the allocation of machine-to-operation qualifications in a semiconductor wafer fabrication photolithography workstation is employed to illustrate this problem. Factory performance, as achieved by both conventional and optimal means, is compared via simulations of a model of a semiconductor wafer fabrication facility. The improvement, in factory performance–and estimated cost savings–was found to be substantial.

ACO-based multi-objective scheduling of parallel batch processing machines with advanced process control constraints

This research was motivated by a scheduling problem in the dry strip operations of a semiconductor wafer fabrication facility. The machines were modeled as parallel batch processing machines with incompatible job families and dynamic job arrivals, and constraints on the sequence-dependent setup time and the qual-run requirements of advanced process control. The optimization had multiple objectives, the total weighted tardiness (TWT) and makespan, to consider simultaneously. Since the problem is NP-hard, we used an Ant Colony Optimization (ACO) algorithm to achieve a satisfactory solution in a reasonable computation time. A variety of simulation experiments were run to choose ACO parameter values and to demonstrate the performance of the proposed method. The simulation results showed that the proposed ACO algorithm is superior to the common Apparent Tardiness Cost-Batched Apparent Tardiness Cost rule for minimizing the TWT and makespan. The arrival time distribution and the number of jobs strongly affected the ACO algorithm’s performance.

Integrating a decomposition procedure with problem reduction for factory scheduling with disruptions: a simulation study

Dispatching rules are widely used in industry because schedules obtained from optimization procedures can be difficult to implement in the face of executional uncertainties. Barua et al. (Barua, A., Narasimhan, R., Upasani, A. and Uzsoy, R., Implementing global factory schedules in the face of stochastic disruptions. Int. J. Prod. Res., 2005, 43(4), 793–818) implement global schedules obtained from an optimization-based heuristic using a dispatching rule, and outperform myopic dispatching rules in the face of disruptions. However, the computation of the global schedules is still time-consuming for realistic instances. Upasani et al. (Upasani, A., Uzsoy, R. and Sourirajan, K., A problem reduction approach for scheduling semiconductor wafer fabrication facilities. IEEE Trans. Semicon. Manuf., 2006, 19, 216–225) develop a problem reduction scheme based on load disparity between work centres, and report significant reduction in CPU times with minimal loss of solution quality in deterministic experiments. In this paper we integrate the problem-reduction scheme to obtain global schedules with the dispatching approach of Barua et al. (Barua, A., Narasimhan, R., Upasani, A. and Uzsoy, R., Implementing global factory schedules in the face of stochastic disruptions. Int. J. Prod. Res., 2005, 43(4), 793–818) in a multi-product environment with stochastic machine breakdowns and job arrivals. A simulation model of a scaled-down wafer fabrication facility is used to evaluate the performance of the proposed procedures. Results show that the integrated procedure outperforms the benchmark dispatching rules while significantly reducing computation times.

A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy. </para>

A due-date based production control policy using WIP balance for implementation in semiconductor fabrications

Production control policies are critical in the re-entrant processes of semiconductor fabrication. Manufacturing control policies such as input dispatching rules, CONWIP, and optimization-based rules have been implemented according to the managerial objectives of the wafer fabrication line. When few semiconductor wafer fabrication facilities were available, and the semiconductor industry was a seller's market, fabrications were operated to achieve both a high rate of production and high utilization of equipment. With the availability of more fabrications and the gradual shift to a buyer's market, customer satisfaction became a major measure of performance in semiconductor manufacturing. In this paper, due-date based production control policies for semiconductor fabrications are suggested, and their performances evaluated. Target balance (TB) optimization models using production target, due-dates, and WIP (work-in-process) are presented. The evaluation result shows that the TB models perform better than the ones cited in the literature.