Bi-criteria parallel batch machine scheduling to minimize total weighted tardiness and electricity cost

Jens Rocholl,John Fowler,Lars Mönch

doi:10.1007/s11573-020-00970-6

Abstract

A bi-criteria scheduling problem for parallel identical batch processing machines in semiconductor wafer fabrication facilities is studied. Only jobs belonging to the same family can be batched together. The performance measures are the total weighted tardiness and the electricity cost where a time-of-use (TOU) tariff is assumed. Unequal ready times of the jobs and non-identical job sizes are considered. A mixed integer linear program (MILP) is formulated. We analyze the special case where all jobs have the same size, all due dates are zero, and the jobs are available at time zero. Properties of Pareto-optimal schedules for this special case are stated. They lead to a more tractable MILP. We design three heuristics based on grouping genetic algorithms that are embedded into a non-dominated sorting genetic algorithm II framework. Three solution representations are studied that allow for choosing start times of the batches to take into account the energy consumption. We discuss a heuristic that improves a given near-to-optimal Pareto front. Computational experiments are conducted based on randomly generated problem instances. The varepsilon -constraint method is used for both MILP formulations to determine the true Pareto front. For large-sized problem instances, we apply the genetic algorithms (GAs). Some of the GAs provide high-quality solutions.

Highlights

Semiconductor manufacturing deals with producing integrated circuits (ICs) on wafers, thin discs made of silicon or gallium arsenide
We propose heuristic approaches for the bi-criteria scheduling problem that are based on grouping genetic algorithms (GGAs) that are embedded into a non-dominated sorting genetic algorithm (NSGA) II-type framework
We show that the -constraint method can be used to compute the entire set of Pareto-optimal schedules for medium-sized problem instances of a special case of the general scheduling problem

Summary

Introduction

Semiconductor manufacturing deals with producing integrated circuits (ICs) on wafers, thin discs made of silicon or gallium arsenide. Wafer fabs can be modeled as a job shop with a couple of unusual features such as a large number of machine groups with machines that offer the same functionality, reentrant process flows, (i.e., some of the machine groups are visited by the same job many times), and a mix of single wafer, lot, and batch processing (Mönch et al 2013). Since batch processing machines process several jobs at the same time, they tend to offload multiple lots on machines that are able to process only single wafers or jobs. This leads to long queues in front of these serial machines. Scheduling batch processing machines in an appropriate manner is crucial for the overall performance of a wafer fab (Mönch et al 2011)

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