Semiconductor Random Access Memory Research Articles

A 16-level-cell memory with c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide FET using threshold voltage cancel write method

We demonstrate a 16-level cell using a nonvolatile oxide semiconductor random access memory test chip based on c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide (CAAC-IGZO) FETs. The memory cell consists of a CAAC-IGZO FET, a p-channel metal–oxide–semiconductor Si FET, and a cell capacitor. Data are written using a threshold voltage cancel write method, and a read circuit composed of voltage followers outputs a read voltage. Using a 200 ns write time of the test chip, the obtained maximum read voltage distribution width is 37 mV in the case of 32768 memory cells. The distributions of 16 read voltages are separated from each other without overlapping, with a single voltage follower exhibiting a maximum read voltage distribution width of 25.3 mV. In the −40 to 85 °C temperature range, the voltage distribution range is 0.13 V, and the variation due to varying temperatures is 0.24 mV/°C.

Fabrication of dynamic oxide semiconductor random access memory with 3.9 fF storage capacitance and greater than 1 h retention by using c-axis aligned crystalline oxide semiconductor transistor with L of 60 nm

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

(Invited) Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

Multilevel cell nonvolatile memory has been developed with a field-effect transistor (FET) containing a crystalline oxide semiconductor (OS), specifically c-axis aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO). The memory is called nonvolatile oxide semiconductor random access memory (NOSRAM). A NOSRAM cell consists of a CAAC-IGZO FET, a p-channel MOS (PMOS) transistor, and a cell capacitor. We have demonstrated that a single 3-bit NOSRAM cell has an endurance of 1012 cycles and a write time of 5 ns. The 6σ tolerance for cell V th distribution of a test chip including an 18-kbit NOSRAM cell array is 109 mV. The test chip achieves a 3-bit/cell NOSRAM.

Crystalline Oxide Semiconductor Using CAAC-IGZO and its Application

We have been researching crystalline InGaZn-oxide (IGZO) and found c-axis aligned crystal (CAAC) structure and nano crystal (nc) structure [1,2]. Examining the CAAC-IGZO film in detail, we found 1-3 nm thin pellet structures (hereinafter, pellets) aligned on a substrate, parallel to each other. As for the nc-IGZO film, we found that pellets are aligned randomly. Commercial production utilizing these structures has already been started. A paper arguing an IGZO film with amorphous structure has been published in 2004 [3, 4]. The authors of the paper define the amorphous structure [5]. Following the definition, we conducted reproductive experiments of amorphous-IGZO (a-IGZO). As a result, we found crystalline structure existing at least in a part of the film described as a-IGZO, but such amorphous structure as defined by them was not confirmed. Accordingly, we believe that a crystalline structure of (Ga,Zn)O/InO2/(Ga,Zn)O which is a basic homologous structure is necessarily formed, that is, the amorphous structure is not formed at the time of film formation by sputtering. We analyzed in detail the film prepared under the same processing conditions as a-IGZO, which we call amorphous-like IGZO (a-like IGZO) film, and found from cross-sectional TEM images that the film macroscopically had many voids grown in a direction perpendicular to the substrate (Fig. 1). We also found from TDS measurement that the film contained much water. Since TFTs using the film have a large variation of I d-V g characteristics as shown in Fig. 1, it is expected that practical use of such TETs is impossible. On the other hand, we confirmed that the density of a CAAC or nc-IGZO film became close to that of a single crystalline IGZO film of 6.357 g/cm3 by reducing water and hydrogen content in the film. This can lead to a highly reliable crystalline IGZO film with stable FET characteristics. In addition, we tested the effect of electron-beam irradiation on each of a-like IGZO, nc-IGZO and CAAC-IGZO films. As a result, we found that crystallization proceeded only in the a-like IGZO film and the a-like IGZO became unstable whereas the nc-IGZO and CAAC-IGZO films remained unchanged and stable. Since basic materials for commercial products need to be durable and stable, CAAC structure is considered most suitable. CAAC-IGZO is applied to not only displays but also LSIs. Examining frequency characteristics with a scale of channel length L = 60 nm, we obtained a cutoff frequency of 2 GHz, and in a memory cell with a capacitance of 1 fF, we achieved a nanosecond-order writing time. Furthermore, we succeeded in lowering I off of FET with the channel length of 0.8 μm to 1 yA/μm (1 × 10- 24 A/μm) under the condition of 85 °C. We are opening the new possibility of nonvolatile oxide semiconductor random access memory (NOSRAM, flash memory that endures 1012-time or more rewrites without deterioration), extremely-low power consumption of normally-off CPU, and incorporation of NOSRAM with other memories in CPU. The details will be discussed in our presentation. REFERENCES[1] S. Yamazaki, J. Koyama, Y. Yamamoto, and K. Okamoto, SID Symposium Digest 43 (2012) 183.[2] S. Ito, E. Takahashi, K. Dairiki, M. Oota, T. Hirohashi, M. Takahashi, M. Tsubuku and S. Yamazaki, Proc. AM-FPD’13 Dig. Tech. Pap. (2013) 154.[3] K. Nomura, H, Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, Nature 432 (2004) 488.[4] K. Nomura, T. Kamiya, H. Ohta, T. Uruga, M. Hirano, and H. Hosono, Phys. Rev. B75 (2007) 035212.[5] T. Kamiya, K. Kimoto, N. Ohashi, K. Abe, Y. Hanyu, H. Kumomi, and H. Hosono, IDW’13 Proceedings AMD2-5L.

Tunneling-based SRAM

This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced. Experimental results for a compound semiconductor 1-bit 50-nW TSRAM gain cell using low current density (/spl sim/1 A/cm/sup 2/) RTDs and low-leakage heterostructure field effect transistors are presented. We describe a one-transistor TSRAM cell which could convert silicon dynamic RAM (DRAM) to ultradense SRAM if an ultralow current density (/spl sim/1 /spl mu/A/cm/sup 2/) silicon bistable device is developed. Finally, we present experimental and simulation results for a TSRAM cell using multipeaked I-V curve devices and a multivalued word line. This approach aims at increasing storage density through vertical integration of bistable devices such as RTD's.

Reliability of semiconductor RAMs with soft-error scrubbing techniques

Error control codes are widely used to improve the reliability of random-access memory (RAM) systems. The paper evaluates the reliability of coded memory systems suffering both hard (permanent) errors and soft (transient) errors. The technique of soft error scrubbing, that is periodically removing all soft errors to improve the system reliability, is studied for RAM systems with chip-level coding only (one-level fault tolerance) and both board-level and chip-level codings (two-level fault tolerance). Previous work, which covers hard errors only, is extended to include the technique of soft-error scrubbing. In addition, the assumption that the error rates among the different memory components are the same is removed. The result offers a simple and low-computational way of estimating the reliability of semiconductor RAMs protected by the error control codes.

AN EFFICIENT TEST PROCEDURE FOR FUNCTIONAL FAULTS IN SEMICONDUCTOR RANDOM ACCESS MEMORIES

This paper proposes a new procedure for testing semiconductor random access memories (RAMs). The test procedure detects simultaneously present functional faults such as stuck-at faults, transition faults and coupling faults and requires 19N operations, which is an improvement over conventional procedures. Thus testing time is reduced by the smaller number of operations of the test procedure, test generation and applications are simplified by the linear address marching.

Morphology of uranium precipitates in silicon

Soft errors induced by incident alpha particles have been observed in dynamic Metal-Oxide- Semiconductor Random Access Memory (MOS RAMs), charge coupled devices (CCDs), static MOS RAMs and in bipolar RAMS. The focus of attention has been the occurrence of soft errors as a result of alpha particle decay of uranium present even in trace amounts, typically a few ppm (parts per million), in the silicon substrate along with the devices as well as the packaging material. A study of segregation of uranium in silicon is of special interest since a single alpha particle of approximately 40 MeV that has a track length of about 20 μ in silicon can give rise to nearly 106 electron-hole pairs if all the deposited energy is converted to the generation of excess carriers. If these excess carriers are developed in a critical volume depending upon the density of devices in a product, the effect can be large enough to limit the mean time of failure to a few days or weeks for a 64k memory cell. In order to study the diffusion and segregation characteristics of uranium in silicon, uranium was deliberately ion implemented into bare silicon to a dose of 1014/cm2 and subsequently annealed at several temperatures often encountered in device processing. In this paper, we present TEM results especially pertaining to the morphology of uranium precipitates in silicon. Conventional microstructural observations, using bright field (BF) imaging, stereographic projection analysis using electron diffraction patterns, and projected directions of the precipitate with respect to matrix reflection from silicon onto a stereogram, and moire patterns using phase contrast imaging, were used to determine the morphology of fine uranium precipitates in ion implanted and annealed samples.

VLSI semiconductor random access memory functional testing

An overview of VLSI testing is presented, using Random access memory (RAM) chip functional testing procedures Marching and GALPAT. A revised GALPAT test procedure is developed for RAM chips. An important aspect of each test procedure is to detect permanent faults in the RAM chip. Functional-level fault models for RAMs, are described. Details of the set-up of an automated VLSI test-station for the Marching, GALPAT and Revised GALPAT tests on the Intel 2114A-5 1 K static RAM are presented. Technical difficulties during Intel 2114A-5 chip testing are highlighted. The fault coverage and execution time of each test procedure are discussed.

Linear sum codes for random access memories

Linear sum codes (LSCs) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories (RAMs). They use the natural addressing scheme found on RAMs to form and access codewords with a minimum of overhead. The authors formally define linear sum codes and examine some of their characteristics. Specifically, they examine their minimum distance characteristics, their error correcting capabilities, and the complexity involved in their implementation. In addition, detailed consideration is given to an easily implemented class of single-, double-, and triple-error correcting LSCs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Built—in concurrent testing for semiconductor random access memories by concurrently testing cells on a word‐line

AbstractWith the recent development of high‐density logical circuits with complex functions, a problem is produced in the long time for the functional testing. One method to cope with this problem is to employ builtin testing, which is one of the designs for testability. The method includes the testing circuit in the IC chip (the circuit under test), and testing is performed by the chip itself to decide whether or not the function is normal. We have already proposed new built‐in testing, which can test concurrently all memory cells on a word‐line. The pattern‐sensitive fault is one of the faults which have been difficult to detect. This paper applies the previously proposed method to such a fault, and presents the result. Using the method in this paper, testing can be performed by the near‐optimal test sequence with the complexity of 302N1/2, which is a drastic decrease compared with other testing methods reported to date. The testing circuit can easily be constructed using counters and shift‐registers. The hardware overhead as evaluated by the equivalent number of gates is almost negligible when the memory capacity is increased.

A built‐in test for functional testing in semiconductor random access memory

AbstractThe increasing time for functional testing of the logical circuit has become a problem in recent years. As a solution a built‐in test is proposed as a means to make testing easier. In the proposed method, the testing circuit is built in the IC chip, and the test is executed within the chip to verify whether the function is fault‐free. This paper proposes a new built‐in test for the semiconductor memory by considering its internal operation. In the method, all the data from memory cells on the same word‐line can be treated at the same time, using the built‐in test circuit in the chip. As a result, the length of the test sequence is of the order of N1/2, realizing a high‐speed testing. Another feature is that the tests for the memory‐cell array and the decoder can be executed independently, making it possible to cope with the multiple fault in those circuits. The built‐in test circuit can be implemented in a relatively simple way, and the extra hardware overhead becomes almost negligible with the increase of the memory capacity.

An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories

This paper presents an efficient test procedure for the detection of simultaneously present functional faults in semi-conductor random access memories (RAM's). The proposed procedure detects modeled types of functional faults using 36N + 24N log 2 N operations, which is an improvement over existing techniques. The testing process is twofold: first, it detects simple functional faults by a linear address marching. Second, it detects more complex types of functional faults by a nonlinear address sequencing approach. Simulation results to support the testing procedure are also presented.

Functional Testing of Semiconductor Random Access Memories

This paper presents an overview of the problem of testing semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are &scussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults. Test procedures for these fault models are presented and their fault coverage and execution times are discussed. The paper is intended for the general computer scmnce audience and presupposes no background in the hardware testing area.

A novel associative approach for fault-tolerant MOS RAMs

A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well.

A March Test for Functional Faults in Semiconductor Random Access Memories

A test procedure requiring 14 N operations to detect functional faults in semiconductor random access memories (RAM's) is given. It is shown that the proposed test procedure detects modeled types of functional faults if only one type of fault is present in the RAM under test. The test procedure given belongs to a class of tests called march tests. It is proved that any march test requires at least 14 N operations to detect the modeled faults. Next, groups of different types of functional faults that can be simultaneously present in the RAM under test and yet be detected by the proposed test procedure or a given enhanced test procedure (requiring 16 N operations) are studied.

Economical realisation of asynchronous sequential circuits using random-access memories

This paper shows that by taking advantage of a fairly uniform delay distribution in semiconductor random-access memories (ROMs and read-write memories in integrated circuit form) it is possible to realise asynchronous sequential circuits (ASCs) economically. It is shown that the ASC so designed will function without fault, in spite of the presence of races and essential hazards in the ASC.

Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories

A class of pattern-sensitive faults in semiconductor random-access memories are studied. Efficient test procedures to detect and locate modeled faults are presented.

Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Furthermore, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count.

Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate size memory systems applicable to microcomputer systems. Design objectives included low cost, adequate performance, reliable operation, small size, and low power consumption as well as simple interfacing to standard microprocessors. A simple two-level organization employing a random access memory (RAM) to buffer the serial CCD memory was used to improve the memory system performance and to simplify the interfacing of microcomputers. It is anticipated that the memory system can be easily modified to use 64 kbit and larger CCD memory devices as these become available. Further more, the memory system control logic could be integrated on a single large-scale integration (LSI) chip, thereby facilitating the fabrication of relatively large and economical memory systems with a low component count.