A built‐in test for functional testing in semiconductor random access memory

Abstract

AbstractThe increasing time for functional testing of the logical circuit has become a problem in recent years. As a solution a built‐in test is proposed as a means to make testing easier. In the proposed method, the testing circuit is built in the IC chip, and the test is executed within the chip to verify whether the function is fault‐free. This paper proposes a new built‐in test for the semiconductor memory by considering its internal operation. In the method, all the data from memory cells on the same word‐line can be treated at the same time, using the built‐in test circuit in the chip. As a result, the length of the test sequence is of the order of N1/2, realizing a high‐speed testing. Another feature is that the tests for the memory‐cell array and the decoder can be executed independently, making it possible to cope with the multiple fault in those circuits. The built‐in test circuit can be implemented in a relatively simple way, and the extra hardware overhead becomes almost negligible with the increase of the memory capacity.