A 16-level-cell memory with c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide FET using threshold voltage cancel write method

Abstract

We demonstrate a 16-level cell using a nonvolatile oxide semiconductor random access memory test chip based on c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide (CAAC-IGZO) FETs. The memory cell consists of a CAAC-IGZO FET, a p-channel metal–oxide–semiconductor Si FET, and a cell capacitor. Data are written using a threshold voltage cancel write method, and a read circuit composed of voltage followers outputs a read voltage. Using a 200 ns write time of the test chip, the obtained maximum read voltage distribution width is 37 mV in the case of 32768 memory cells. The distributions of 16 read voltages are separated from each other without overlapping, with a single voltage follower exhibiting a maximum read voltage distribution width of 25.3 mV. In the −40 to 85 °C temperature range, the voltage distribution range is 0.13 V, and the variation due to varying temperatures is 0.24 mV/°C.