Built—in concurrent testing for semiconductor random access memories by concurrently testing cells on a word‐line

Abstract

AbstractWith the recent development of high‐density logical circuits with complex functions, a problem is produced in the long time for the functional testing. One method to cope with this problem is to employ builtin testing, which is one of the designs for testability. The method includes the testing circuit in the IC chip (the circuit under test), and testing is performed by the chip itself to decide whether or not the function is normal. We have already proposed new built‐in testing, which can test concurrently all memory cells on a word‐line. The pattern‐sensitive fault is one of the faults which have been difficult to detect. This paper applies the previously proposed method to such a fault, and presents the result. Using the method in this paper, testing can be performed by the near‐optimal test sequence with the complexity of 302N1/2, which is a drastic decrease compared with other testing methods reported to date. The testing circuit can easily be constructed using counters and shift‐registers. The hardware overhead as evaluated by the equivalent number of gates is almost negligible when the memory capacity is increased.