Applications In Semiconductor Manufacturing Research Articles

Call for Papers for Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing

Call for Papers for Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing

Call for Papers for Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing

Call for Papers for Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing

Machine learning virtual SEM metrology and SEM-based OPC model methodology

Background: E-beam metrologies, both critical dimension scanning electron microscope metrology and defect scan metrology, have been playing a very critical role in gating patterning quality. SEM images can provide rich visual information for engineers to do qualitative and quantitative analyses. However, the low e-beam metrology tool throughput makes it impossible to obtain SEM images for larger area. Monte Carlo-based SEM image simulations or other SEM image simulations require postlithography or postetch pattern three-dimensional structures as prerequisite, and the simulation speed is not sufficiently fast for full chip implementation. Aim: We aim to develop machine learning SEM models with sufficient accuracy and speed for full chip application in semiconductor manufacturing environment. Approach: We have proposed a virtual SEM metrology solution based on U-Net neural network with physics-based feature maps as model input. With information in aerial image space encoded properly, SEM images of both postlithography and postetch can be predicted accurately enough for practical applications using our proposed virtual SEM metrology models. Equipped with GPUs, the machine learning-based SEM image models are fast enough to make it possible to realize full chip SEM generation from post-OPC data. Results: Our machine learning SEM image models can predict SEM images with normalized cross correlation around 0.95 in reference to ground truth SEM images, each SEM image (512 × 512 in size) takes about 800 ms using single CPU, and the speed can be accelerated to about 10 ms with single GPU. Conclusions: Using U-Net structure and physics-based feature maps as model inputs, machine learning-based SEM image models can be developed. The models are sufficiently accurate and fast to find their applications in semiconductor manufacturing, and they can be used as independent model for OPC data verification or generate SEM images as reference for SEM defect scan metrology.

Polarization-independent 2×2 high diffraction efficiency beam splitter based on two-dimensional grating.

Better performances of two-dimensional (2D) grating are required recently, such as polarization independence, high efficiency, wide bandwidth and so forth. In this paper, we propose a 2×2 2D silver cylindrical array grating with excellent polarization-independent high diffraction efficiency (DE) over communication band for beam splitting. The grating was calculated by rigorous coupled wave analysis (RCWA) and can achieve over 24% DE of four first diffraction orders at 1550 nm with nonuniformity of 1.43% in both transverse electric (TE) and transverse magnetic (TM) polarizations, which is a significant improvement over previous reports. The holographic exposure technology, wet chemical development process and electron beam evaporation were used to fabricate the 2D grating. The correctness and accuracy of the calculation are fully verified with the measurement result of fabricated grating. Excellent performances of the 2D splitter we proposed will have great potential for applications in optical communication, semiconductor manufacturing and displacement measurement.

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on Process-Level Machine Learning Applications in Semiconductor Manufacturing

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on "Process-Level Machine Learning Applications in Semiconductor Manufacturing"

IEEE Transactions on Semiconductor Manufacturing CALL FOR PAPERS for Special Issue on "Process-Level Machine Learning Applications in Semiconductor Manufacturing"

A Review of Data Mining Applications in Semiconductor Manufacturing

For decades, industrial companies have been collecting and storing high amounts of data with the aim of better controlling and managing their processes. However, this vast amount of information and hidden knowledge implicit in all of this data could be utilized more efficiently. With the help of data mining techniques unknown relationships can be systematically discovered. The production of semiconductors is a highly complex process, which entails several subprocesses that employ a diverse array of equipment. The size of the semiconductors signifies a high number of units can be produced, which require huge amounts of data in order to be able to control and improve the semiconductor manufacturing process. Therefore, in this paper a structured review is made through a sample of 137 papers of the published articles in the scientific community regarding data mining applications in semiconductor manufacturing. A detailed bibliometric analysis is also made. All data mining applications are classified in function of the application area. The results are then analyzed and conclusions are drawn.

High-efficiency polarization-independent gold-coated crossed grating under normal incidence

A gold-coated crossed grating (GCCG) is designed and fabricated to improve the signal contrast and signal-noise-ratio (SNR) of the grating interferometer (GI) with the high-efficiency polarization-independent property. The proposed grating based on two dimensional (2D) periodic gold nanocylinder structure can diffract both TE and TM polarizations into four first orders with measured diffraction efficiency (DE) of more than 21.8% and total DE of more than 88.8% at 780 nm incident wavelength under normal incidence, which shows the highest DE and brings much benefits to the SNR and compactness in practical applications. Moreover, the optimized GCCG also shows great tolerances of duty cycle, groove depth, and sidewall angle for grating fabrication. The measured DEs from the experimental results substantiate themselves with the numerical calculations. Additionally, the measured DE of the (±1, 0) order and (0, ±1) order all exceed 18% at the wavelength range from 750 nm to 810 nm and present great polarization independence at the polarization angle varying from 0° to 90°. The experimental results show the excellent performance of GCCG for improving heterodyne grating interferometer and indicate great potential for applications in microscopy techniques, semiconductor manufacturing, and material processing.

Magnetron sputtering

Magnetron sputtering developed rapidly in the 1980s for semiconductor, hard coating, and architectural glass applications. While the general operating principles were well known, subtle issues relating to cathode material, operating parameters, and deposition processes were only empirically understood. A sequence of magnetron measurements is described, which helps develop a more general understanding. The plasma is mostly conventional but is strongly perturbed by the large fluxes of energetic, neutral atoms sputtered from the cathode, which alter the gas dynamics as well as the discharge impedance. These studies have led to practical innovations, such as collimation and ionization of the sputtered atoms, which have been widely used for semiconductor manufacturing applications.

Experimental investigations of the effect of the neutral gas pressure on the separate control of ion energy and flux in dual frequency capacitively coupled plasmas

Classical dual-frequency capacitively coupled plasmas (2f CCPs) operating at low pressures and significantly different frequencies are often used for a variety of applications in semiconductor manufacturing in order to control the mean ion energy at the electrodes separately from the ion flux. However, recent computational studies have indicated that this separate control is limited by the frequency coupling effects and by the contribution of secondary electrons to the ionization dynamics [Donkó et al., Appl. Phys. Lett. 97, 081501 (2010); Schulze et al., Plasma Sources Sci. Technol. 20, 045007 (2011)]. Here, we verify these simulation results experimentally by measuring the ion flux to an electrode as a function of the low frequency (LF) and high frequency power at different neutral gas pressures in a 2f CCP operated at 2.26 MHz and 13.56 MHz in argon. In agreement with previous computational predictions, we find the ion flux to decrease as a function of the LF power at a low pressure of 1 mTorr due to the frequency coupling and to increase as a function of the LF power at a higher pressure of 60 mTorr due to the presence of secondary electrons. These experimental findings show that separate control of ion properties in classical 2f CCPs is generally not possible, but potentially limited to specific discharge conditions.

Role of the dense amorphous carbon layer in photoresist etching

The development of new photoresists for semiconductor manufacturing applications requires an understanding of the material properties that control the material's plasma etching behavior. Ion bombardment at ion energies of the order 100 s of eV is typical of plasma-based pattern-transfer processes and results in the formation of a dense amorphous carbon (DAC) layer on the surface of a photoresist, such as the PR193-type of photoresist that currently dominates the semiconductor industry. Prior studies have examined the physical properties of the DAC layer, but the correlation between these properties and the photoresist etching behavior had not been established. In this work, the authors studied the real-time evolution of a steady-state DAC layer as it is selectively depleted using an admixture of oxygen into an argon plasma. Observations of the depletion behavior for various DAC layer thicknesses motivate a new model of DAC layer depletion. This model also correlates the impact of the DAC layer thickness with the etch rate of the bulk photoresist. The authors find that up to a 40% depletion of the DAC layer thickness does not have a significant impact on the bulk photoresist etch rate. However, further depletion results in an exponential increase in the etch rate, which can be up to ten times greater at full depletion than for the fully formed DAC layer. Thus, with these trends the authors show that the photoresist etch rate is controlled by the thickness of the DAC layer. Furthermore, thickness loss of the DAC layer in an O2-containing plasma coincides with a chemical modification of the layer into an oxygen-rich surface overlayer with properties that are intermediate between those of the DAC layer and the bulk photoresist. Support for this interpretation was provided via x-ray photoelectron spectroscopy characterization. Atomic force microscopy was used to gauge the impact on surface roughness as the DAC layer is formed and depleted. The trends established in this work will provide a benchmark in our development of new photoresists, which will be suitable for pattern transfer processes that will ultimately be a part of enabling smaller semiconductor device feature sizes and pitches.

Electro-Less Deposition Using Metal Ion Based Reducing Agents: Potential Benefits and Applications in Semiconductor Manufacturing

Further miniaturization of interconnects and devices to keep up with Moore’s law in the 21st century requires materials and process innovations. Electroplating, in a dual damascene process flow, has been the workhorse of the semiconductor industry for back-end-of-line metallization for the past two decades. As wire dimensions shrink below 20 nm in future technology nodes, electrochemical deposition faces a few challenges. Good gap-fill of <10 nm structures is increasingly difficult due to 1) the inability of conventional additives to provide bottom-up growth and 2) the terminal effect arising from resistive liners yielding poor nucleation. One process that becomes promising at such dimensions is electro-less deposition1. Electro-less deposition is a selective deposition process that can provide void-free metal fill in small dimensions. Since no external current is applied, electro-less deposition also does not suffer from terminal effects observed in electro-deposition on thin liners. Traditionally, electro-less deposition is performed using a class of reducing agents that include: boranes, hypophosphite, hydrazine etc. These processes have a few drawbacks. Firstly, presence of multi-step oxidation process for the reducing agents makes these systems difficult to study and characterize from a fundamental understanding standpoint2. Secondly, oxidation of the reducing agents often involve incorporation of B, P or H2 in the deposit which is undesirable for interconnect metals that require low resistivity and low stress. Here we present an electro-less deposition process using metal ion reducing agents3,4, specifically trivalent titanium (Ti+3). We show that, in such systems, reduction and oxidation reactions can be studied separately and the overall redox process follows the mixed potential theory4, unlike the traditional electroless processes (Fig. 1). Based on electrochemical studies, electro-less deposition processes were developed logically for a group of metals that include: Cu, Co, Ni and Pt. We show that the resulting metal films are free of any impurities (such as B, P or H2) and possess very low resistivity, similar to those deposited by physical vapor deposition (Fig. 2). Processes were scaled up for deposition on 300 mm diameter wafers and challenges associated with them, particularly substrate pre-treatment and electrolyte stability, are discussed. Finally, few novel applications of such processes in semiconductor manufacturing are highlighted. Figure 1: Measured mixed potential in a complete electro-less bath and those determined from cathodic and anodic polarization curves according to mixed potential theory for metal-ion and non metal-ion reducing agents processes. Figure 2: Sheet resistances of cobalt and nickel films deposited on a Ru/TaN substrate using the Ti+3 based reducing agent. TEM image (inset) shows a representative cross-section of 4-nm thick cobalt film. M. Schlesinger and M. Paunovic, Modern Electroplating, 5th ed., Wiley, New York (2000)J. E. A. M. Van Den Meerakker, J. Appl. Electrochem., 11 (1981)A. Vaskelis, E. Norkus, Electrochim. Acta, 44 (1999)D. L. Rutkevich et al., J. Electrochem. Soc., 140 (1993) Figure 1

Reliability Baseline Management and Applications in Semiconductor Manufacturing

Reliability assessment is very important in semiconductor manufacturing, and we need to setup and maintain an efficient and effective reliability baseline (BL) management system to, for example, assess reliability risks, to dispose impacted lots, and to release equipment. To achieve these goals, we propose a corresponding flow and pinpoint the critical points to establish and maintain reliability BLs. To provide insights to readers by actual cases on reliability BL analyses and applications, we setup and analyze the BLs for the electric-field acceleration factor and activation energy of gate oxide, the gate voltage exponent of device Negative Bias Temperature Instabilities (NBTI), and the parameters of interconnect model for current density and activation energy. We also find the enriched reliability BL database does benefit line excursion disposition, process optimization, quicker judgment on the reliability impacts of nonconformance, feasibility studies of process changes, faster tool releases, risk assessments of common reliability tests, and earlier root cause identifications of abnormality by narrowing down failure mechanisms.

Overview and new results in disturbance observer based adaptive vibration rejection with application to advanced manufacturing

SummaryVibrations with unknown and/or time‐varying frequencies significantly affect the achievable performance of control systems, particularly in precision engineering and manufacturing applications. This paper provides an overview of disturbance‐observer‐based adaptive vibration rejection schemes; studies several new results in algorithm design; and discusses new applications in semiconductor manufacturing. We show the construction of inverse‐model‐based controller parameterization and discuss its benefits in decoupled design, algorithm tuning, and parameter adaptation. Also studied are the formulation of recursive least squares and output‐error‐based adaptation algorithms, as well as their corresponding scopes of applications. Experiments on a wafer scanner testbed in semiconductor manufacturing prove the effectiveness of the algorithm in high‐precision motion control. Copyright © 2015 John Wiley &amp; Sons, Ltd.

An effective procedure for sensor variable selection and utilization in plasma etching for semiconductor manufacturing

Plasma etching processes have a potentially large number of sensor variables to be utilized, and the number of the sensor variables is growing due to advances in real-time sensors. In addition, the sensor variables from plasma sensors require additional knowledge about plasmas, which becomes a big burden for engineers to utilize them in this filed. Thus an effective procedure for sensor variable selection with minimum plasma knowledge is needed to develop in plasma etching. The integrated squared response (ISR) based sensor variable selection method which facilitates collecting and analyzing sensor data at one time with regard to manipulated variables (MVs) is suggested in this paper. The reference sensor library as well as sensor ranking tables constructed on the basis of ISR can give insight into plasma sensors. The ISR based sensor variable selection method is incorporated with relative gain array (RGA) or non-square relative gain array (NRGA) for effective variable selection in building a virtual metrology (VM) system to predict critical dimension (CD) in plasma etching. The application of the technique introduced in this paper is shown to be effective in the CD prediction in plasma etching for a dynamic random access memory (DRAM) manufacturing. The procedure for sensor variable selection introduced in this paper can be a starting point for various sensor-related applications in semiconductor manufacturing.

In Situ Characterization of Triboelectrochemical Effects on Topography of Patterned Copper Surfaces

The topographic response of patterned copper surfaces to chemical–mechanical polishing (CMP) was investigated using a triboelectrochemical approach. Experimental methods include using a combined system containing a tribometer and a potentiostat. Results showed that more step height reduction and lower average surface roughness were obtained via CMP in acidic than in alkaline slurry. The increased contact area between wafer, pad, and abrasives was associated with the increase in friction. It was found that pH-dependent oxide formation and removal dominate the step height reduction for both acidic and alkaline slurries. The in situ approach pinpointed interactions between mechanical stimulation, chemical reaction, and electrochemical passivation. This research is beneficial to understanding triboelectrochemistry in Cu chemical–mechanical polishing of patterned wafers, an important application in semiconductor manufacturing.