Semiconductor Thin-film Transistors Research Articles

A comprehensive density-of-states model for oxide semiconductor thin film transistors

In this paper, a novel and comprehensive density-of-states model is presented to understand the origin of conductivity and the performance of p-type and n-type oxide semiconductor thin film transistors (TFTs). To validate the model, the simulated I–V characteristics are compared with measured results of p-type Cu2O and SnO and n-type SnO2 TFTs. It was observed that cation vacancies are responsible for hole conduction in p-type TFTs, while anion vacancies and/or metal interstitials are responsible for electron conduction in n-type TFTs. This was observed by assigning the cation vacancies to acceptor-like Gaussian states and anion vacancies and/or metal interstitials to donor-like Gaussian states. The characteristic slopes in conduction/valence band-tail states are due to disorders present in the oxide semiconductors. The model successfully delivers the physical insight and pathway to circuit simulation of large-scale integration of pixel circuits in active matrix liquid crystal display/active matrix organic light-emitting diodes.

Low-Temperature Solution-Processed n-Channel SnO2 Thin-Film Transistors and High-Gain Zero-VGS-Load Inverter

Low-cost inorganic solution processing for oxide semiconductor thin-film transistors (TFTs) is crucial for developing next-generation cost-effective, ubiquitous, and flexible electronics, and the d...

Slot-die coating of silicon ink for volume production of CMOS polysilicon TFTs

A large-area polysilicon film was formed from slot-die coating of cyclopentasilane based silicon ink and laser crystallization. In this article a study of silicon ink preparation and selection, slot-die coater setup, coating and laser crystallization is described. The polysilicon film was applied to fabricate complementary metal oxide semiconductor (CMOS) thin film transistors (TFTs) which were used to develop and demonstrate near field communication devices. This was part of a hybrid process flow consisting of conventional lithography and printing to fabricate CMOS TFTs. Slot-die coating of silicon ink on a 300 mm square 100 μm thick stainless steel substrate is a key building block of this hybrid process flow to subtract and replace high capital cost plasma enhanced chemical vapor deposition (PECVD), ion implantation and silicon wafers. With slot-die coating of silicon ink, a silicon layer formation equivalent to PECVD in quality was achieved.

34.1: Invited Paper: Availability of a‐IGZO semiconductor TFT in the large size Gen. 11 facilities for competitive high‐end applications

We investigated the four‐phase amorphous‐InGaZnO (a‐IGZO) thin film transistors (TFTs) in the world largest generation 11 factory (Gen.11, 2940mm × 3370mm) which has the cost advantage for future high‐end applications compared to generation 8.5 (Gen. 8.5, 2200mm × 2500mm). Self‐aligned coplanar structure TFT has been developed for large size inkjet printing (IJP) OLED display, and 4 mask back channel etched (BCE) type TFT has been developed for large size 8K4K LCD applications. For the purpose of low cost, high‐end applications, the availability of large size oxide TFT is essential in Gen. 11.

Effects of atmosphere composition during direct ultraviolet-light patterning of solution-deposited In2O3 thin film transistors

Sol-gel synthesis is widely used to fabricate metal oxide thin films by solution, but it requires high-temperature thermal annealing to fully convert precursors to metal oxides. Exposure to Ultraviolet (UV) light before thermal annealing of precursor films has been shown to reduce the conversion temperature, with the added benefits of film patterning when done through a shadow mask and improved device performance. However, the mechanism by which UV exposure under different atmospheric compositions affects the properties of metal oxide films after thermal annealing has not been investigated. Here, we control the atmospheric composition during UV-patterning—prior to high-temperature thermal annealing—of In2O3 sol-gel films which serve as the semiconductor in thin-film transistors. Despite all films being annealed at 250°C in air after UV patterning, films exposed to UV under oxygen-containing atmospheres have higher metal-oxygen-metal bonding and exhibit higher transistor mobility compared to the films exposed to UV under N2 atmosphere. The origin of the effect of atmospheric composition on mobility is studied through X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared spectroscopy and is revealed to be the result of the reformation of the nitrate species in the films under more oxidizing atmospheres during UV exposure. These nitrates can be completely removed by thermal annealing, facilitating more complete metal-oxygen-metal bond formation, which is reflected in higher OI XPS signal and transistor mobility. In contrast, films processed under N2 atmosphere during UV exposure contain nitrite species that cannot be removed by thermal annealing, resulting in less metal-oxygen-metal bond formation and lower mobility.

Mechanisms of Carrier Density Increase of Ternary Cation-Based Amorphous Oxide Semiconductors for Thin Film Transistor Applications

Amorphous oxide semiconductor (AOS) thin film transistors (TFTs) based on In2O3 have attracted much interest for use as pixel switching elements in next generation active-matrix liquid crystal (AM-LCD) and active-matrix organic light emitting diode (AM-OLED) displays. The high field effect mobility of In2O3-based AOS devices (10–25 cm2/Vsec) offers significant performance improvements over present-day a-Si TFTs (<1 cm2/Vsec) technology. Additional advantages of AOS materials include low temperature processing (RT–300 °C), isotropic wet etch characteristics, and high optical transparency (>85 % in the visible regime) all of which make this material suitable for large area, flexible, and transparent devices on inexpensive polymer substrates.There have been considerable efforts to incorporate AOSs into devices, particularly in current-driven active matrix displays such as organic light emitting diode displays as pixel-driving switching elements. Strategies to enhance amorphous phase stability, reduce bias stress-induced threshold voltage shifts, and suppress channel carrier densities have been studied and successfully applied to the switching TFT application. Third cation elements are often added to binary cation oxide systems to limit the channel carrier generation for TFT channel application. We have recently reported that the addition of Al to InZnO, a typical binary cation material system leads to enhanced amorphous phase stability, carrier suppression capability and higher carrier mobility, up to ~45 cm2/Vs (Hall Effect mobility) and ~20 cm2/Vs (field effect mobility)1. All of these characteristics are expected to be a key enabler for realizing the next generation ultra-high-definition displays.Post-process annealing is widely employed in AOS-based TFT fabrication since annealing has been shown to improve field effect mobility2-3 and channel/metallization contacts4-5 as well as reduce trap density6, which often leads to unstable device performance or unfavorable hysteresis in their transistor characterstics6-7. However, the post-annealing is often accompanied by an increase in channel carrier density that induces an unfavorable increase in the device off-state current and operation voltages2, 8. To date, the origin of the increase in channel carrier density has not been fully understood.The current study aims to identify the origin of an increase in carrier density after low-temperature annealing conducted in air, particularly for a third-cation AOS system of InAlZnO (IAZO). Through work function investigations and bandgap analysis, the carrier density of IAZO is found to be increased by > 104 times compared to that of unannealed IAZO after low temperature annealing at 200 °C in air. Photoelectron spectroscopic studies reveal that the typical intrinsic (vacancy-based native defect) or extrinsic (cation substitution) doping mechanisms are not the primary cause of the channel carrier increase. From high pressure oxidation with much enhanced reactivity of reaction gases, it is identified that the equilibrium carrier density of IAZO is much higher than those used in typical TFT channel application. The low channel carrier density tends to increase and reach the higher equilibrium carrier density in the absence of kinetic constraints. The combinatorial investigations presented herein help understand the origin of unintentional increase in channel carrier density in amorphous oxides and its effect on the operation of TFTs.The authors gratefully acknowledge the financial supports of the U.S. NSF Award No. ECCS-1931088; the Purdue Research Foundation (Grant No. 60000029); and the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS.References Reed et al. Journal of Materials Chemistry C 2020, 8 (39), 13798-13810.Nomura et al. Applied Physics Letters 2009, 95 (1), 013502.Lee et al. Thin Solid Films 2012, 520 (10), 3764-3768.Shimura et al. Thin Solid Films 2008, 516 (17), 5899-5902.Lee et al. Journal of Applied Physics 2011, 109 (6), 063702.Ide et al. physica status solidi (a) 2019, 216 (5), 1800372.Liu et al. Journal of the American Chemical Society 2010, 132 (34), 11934-11942.Lee et al. Applied Physics Letters 2014, 104 (25), 252103.

Enhanced Phase Stability and Carrier Suppression of Ternary Cation-Based Amorphous Oxide Semiconductor Thin Film Transistors

Transparent optoelectronic materials have gained significant attention for application in high performance devices such as next generation displays1-2, photovoltaics3, electrochromic devices4, and sensors5-6. Metal oxide-based semiconductors, specifically, are a promising group of transparent optoelectronic materials, now considered to be the vital building blocks for future device applications due to the unique combined properties of excellent optical transparency (from the visible to near-infrared regime), and high electrical conductivities7-8. Metal oxides have already seen wide implementation in various optoelectronic devices, depending on their electrical conductivity, as transparent electrodes by degenerately-doped oxides such as indium tin oxides (ITO) and doped zinc oxides (ZnO), as semiconducting active layers based on In2O3, ZnO or SnO2, and as insulators (e.g., SiO2, Al2O3, HfO2) for dielectrics or encapsulations.The key pixel driving switches in display technologies, thin film transistors (TFTs), require a vast array of demanding material properties such as high carrier mobilities (usually defined as the “TFT field effect mobility”), low thermal budgets during processing, resilient phase stability, and reliable device performance under high thermal and bias stress conditions. Amorphous oxide semiconductors (AOSs), specifically those based on indium oxides, are receiving unique attention for TFT implementation due to their promisingly high carrier mobilities (> 5-20 cm2/Vs) compared to conventional amorphous Si (<~1 cm2/Vs), low processing temperature requirements (ambient to 200 °C), superior mechanical flexibility to their crystalline counterparts, and large area process-ability. Indium oxide-based binary and ternary cation material systems show tremendous promise for use in next generation displays as these materials exceed the aforementioned material property and fabrication requirements. Unfortunately, undoped In2O3 experiences a rapid onset of microstructural crystallization at very low homologous temperatures (T/Tm<0.19) at 150 °C and struggles to maintain its amorphous phase structure. The inclusion of Zn in In2O3 has revealed a viable and promising binary cation material which specifically addresses the structural instability of undoped In2O3, Indium Zinc Oxide (IZO), as the addition of Zn into In2O3 proves to stabilize the temperature-sensitive amorphous phase of indium oxide. Furthermore, the reported carrier mobility of IZO has shown to be as high as 20-40 cm2/Vs for both Hall and 15-30 cm2/Vs for TFT field effect mobilities. Studies have dug deeper to further unveil the effects of doping of In2O3-basd materials, and the ternary cation system of indium gallium zinc oxides (IGZO) has proven to be even more popular than binary systems as the addition of Ga in IGZO allows for the controllable suppression of channel carrier density during TFT applications (preferred for TFT devices where a low device off-state current is desired). In addition to Ga, more third cation species have been investigated as suitable material candidates such as Hf, Si, and Zr, but the carrier mobilities (~3-10 cm2/Vs) are around 3-10 times lower than that of In2O3 or IZO.Therefore, securing strategies to develop a material system which maintains both high carrier mobility (e.g., >~20 cm2/Vs) and suppresses carrier generation for TFT channel application is of significant importance, and is necessary to expedite the realization of next-generation transparent displays which possess reliable performance, fast switching speed, and, consequently, ultra-high definition resolution. In this study, the ternary cation oxide system of indium aluminum zinc oxide (IAZO) is investigated with varying Al concentration in IAZO thin films. The IAZO thin films were deposited using magnetron co-sputtering at room temperature. The structural, optical, and electrical properties were systematically characterized as a function of Al concentration and compared to baseline IZO samples. The carrier transport characteristics, as well as the dominant mechanisms for carrier density and resistivity and their relation to Al concentration, are discussed. Furthermore, amorphous IAZO-based TFTs were developed to objectively compare and validate device performance and parameters against IZO-based TFTs.The authors gratefully acknowledge the financial supports of the U.S. NSF Award No. ECCS-1931088; the Purdue Research Foundation (Grant No. 60000029); and the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 20011028) by KRISS.References Nomura et al. Nature 2004, 432 (7016), 488-492.Lee et al. Applied Physics Letters 2014, 104 (25), 252103.Fortunato et al. MRS Bull. 2007, 32 (3), 242-247.Maho et al. Journal of The Electrochemical Society 2017, 164, H25-H31.Venkatanarayanan et al. Elsevier: Oxford, 2014; pp 47-101.Zhao et al. The Journal of Physical Chemistry C 2015, 119 (26), 14483-14489.Lewis et al. MRS Bull. 2000, 25 (8), 22-27.Coutts et al. MRS Bull. 2000, 25 (8), 58-65. Figure 1

The Investigation of Indium-Free Amorphous Zn-Al-Sn-O Thin Film Transistor Prepared by Magnetron Sputtering

The indium-free amorphous oxide semiconductor thin film transistor (AOS-TFT) with aluminum (Al) electrodes shows broad application prospects in new-generation display technologies, such as ultra-high definition large-screen display, OLED display and 3D display. In this work, the thin film transistor (TFT) with a zinc-aluminum-tin-oxide (ZATO) semiconductor as the active layer and an Al electrodes as the source and drain (S/D) was investigated. The optical, electrical and semiconductive properties of the ZATO films were evaluated by atomic force microscopy (AFM), ultraviolet–visible spectrophotometry and microwave photoconductivity decay (μ-PCD), respectively. The result shows that the film is smooth and transparent and has low localized states and defects at a moderate oxygen concentration (~5%) and a low sputtering gas pressure (~3 mTorr). After the analysis of the transfer and output characteristics, it can be concluded that the device exhibits an optimal performance at the 623 K annealing temperature with an Ion/Ioff ratio of 5.5 × 107, an SS value of 0.15 V/decade and a saturation mobility (μsat) of 3.73 cm2·V−1·s−1. The ZATO TFT at the 623 K annealing has a −8.01 V negative shift under the −20 V NBS and a 2.66 V positive shift under the 20 V PBS.

Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

High-performance amorphous oxide semiconductor thin film transistors (AOS-TFT) with copper (Cu) electrodes are of great significance for next-generation large-size, high-refresh rate and high-resolution panel display technology. In this work, using rare earth dopant, neodymium-doped indium-zinc-oxide (NdIZO) film was optimized as the active layer of TFT with Cu source and drain (S/D) electrodes. Under the guidance of the Taguchi orthogonal design method from Minitab software, the semiconductor characteristics were evaluated by microwave photoconductivity decay (μ-PCD) measurement. The results show that moderate oxygen concentration (~5%), low sputtering pressure (≤5 mTorr) and annealing temperature (≤300 °C) are conducive to reducing the shallow localized states of NdIZO film. The optimized annealing temperature of this device configuration is as low as 250 °C, and the contact resistance (RC) is modulated by gate voltage (VG) instead of a constant value when annealed at 300 °C. It is believed that the adjustable RC with VG is the key to keeping both high mobility and compensation of the threshold voltage (Vth). The optimal device performance was obtained at 250 °C with an Ion/Ioff ratio of 2.89 × 107, a saturation mobility (μsat) of 24.48 cm2/(V·s) and Vth of 2.32 V.

Compositional Engineering of Hf‐Doped InZnSnO Films for High‐Performance and Stability Amorphous Oxide Semiconductor Thin Film Transistors

AbstractThe Hf‐doped indium zinc tin oxide (Hf:InZnSnO) channel for high performance and stable transparent thin film transistors (TFTs) is developed by using a simultaneous cosputtering of InZnSnO and HfO2 targets. The effects of In and Hf composition in Hf:InZnSnO channel on the performance and stability under bias stress for the Hf:InZnSnO channel‐based TFTs are investigated. Herein, the In cations enhance the electrical properties, while the Hf cations reduce the oxygen vacancies in the Hf:InZnSnO channel layer. Adjusting the atomic ratio of In of the InZnSnO target improves the performance of the Hf:InZnSnO‐based TFTs, while introducing an adequate amount of HfO2 improves the bias stabilities and hysteresis characteristics of the Hf:InZnSnO‐based TFTs. The transparent TFT with optimized Hf:InZnSnO channel, with a stoichiometry of Hf0.27In25.96Zn6.99Sn6.16O60.62, that is cosputtered at RF power of 100 W applied to InZnSnO target (In:Zn:Sn = 4:1:1 at%), and RF power of 50 W applied to HfO2 target exhibits a field effect mobility of 11.84 cm2 V−1 s−1 and low shift of threshold voltage of less than 2.5 V under bias stress for 3000 s. The high performance and stability of the Hf:InZnSnO channel‐based TFTs demonstrate the feasibility of transparent TFTs‐related next‐generation display applications.

Solution processed high performance ferroelectric Hf0.5Zr0.5O2 thin film transistor on glass substrate

Thin film transistors (TFTs) with a ferroelectric Hf0.5Zr0.5O2 (HZO) gate insulator (GI) have been reported by using the vacuum process for HZO such as sputtering and atomic layer deposition methods. We report in this paper the ZnO TFT with ferroelectric GI using solution processed AlOx/HZO. AlOx assists in the initiation of ferroelectricity by applying large mechanical stress and provides a sufficient amount of oxygen vacancy to the underlying HZO. X-ray diffraction and capacitance-voltage, polarization-voltage, and anti-clockwise hystereses in the transfer curve confirm the formation of the ferroelectric phase of HZO. The AlOx/HZO TFTs exhibited a field-effect mobility of 140 cm2/V s, an on/off current ratio of 109, and a sub-threshold swing of 0.32 V/decade. The TFT shows a good bias-voltage tunable memory window of ∼4.5 V and memory retention characteristics up to 10 000 s for a programing/erasing voltage of ±10 V with a pulse width of 0.5 s. This work demonstrates the fabrication of ferroelectric HZO TFT using the solution process, and the results can be applied to ferroelectric oxide semiconductor TFT electronics.

(Invited) Atomic Layer Deposited Amorphous Igzo Semiconductor with Vertical Composition Engineering for High Mobility Field Effect Transistor

Amorphous oxide semiconductors have been widely studied for the potential use in flat-panel displays such as active matrix liquid crystal display (LCD) and Organic light emitting didoes (OLEDs). Since reporting amorphous InGaZnO semiconductor thin film transistor (TFT) in 2003 & 2004, many multi-component oxide semiconductors have been intensively investigated and developed by physical vapor deposition (PVD) method. Very recently, the sputtered InGaZnO TFTs are already adopted in mass-production to fabricate AMOLED TVs. Also, semiconductor industries have looked at metal oxide semiconductor thin films as an alternative Si channel layer because this semiconductor exhibited extremely low-off current level (below 10-18A/um). It is the unique property to decrease power consumption for various semiconductor devices. However, there remain several problems such as enhancing field effect mobility, composition uniformity, bias-temperature stability, and p-type oxide semiconductor in order to go further for the future device applications.In this talk, I will introduce various oxide semiconductor materials with atomic layer deposition (ALD) methods. Unlike PVD, ALD method has unique properties, including controlling atomic-level-thickness, manipulating atomic-level-composition control, and depositing impurity-free & uniform films. The key materials such In2O3, ZnO, SnO2, and Ga2O3 will be summarized and then I will show the combinatorial research works in terms of amorphous InGaZnO semiconductor thin film transistors. Generally, electrical properties of amorphous oxide semiconductors are strongly dependent on each element composition. The indium (In) rich InGaZnO exhibited a high mobility of 50cm2/V.sec. However, the In-rich InGaZnO TFTs have the demerit of negative threshold voltage owing to intrinsically high carrier density. I will present that In-rich IGZO TFTs with vertical stacked InOx, ZnOx and GaOx atomic layers show excellent performances such as saturation mobility of ~ 74cm cm2/V.sec, threshold voltage of -1.3V, on/off ratio of 8.9 × 108, subthreshold swing of 0.26V/decade, and hysteresis of 0.2V, while keeping a reasonable carrier density of ~1017 cm-3. Flexible ALD InGaZnO TFTs on polymer substrates were also discussed depending on gate insulator materials, in terms of device performances. ALD technique will be a very promising candidate to improve oxide semiconductor materials as well as various device applications (Display & Semiconductor Industry) because it has not only unique nano-growth mechanism but also ultimate uniform property.

Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs

In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.

Room temperature fabricated high performance IAZO thin film transistors with dual-active-layer structure and sputtered Ta2O5 gate insulator

The room temperature fabrication of amorphous oxide semiconductor thin film transistors (TFTs) is essential for their applications in flexible electronics due to the low glass-transition temperatures of flexible substrates. High performance In-Al-Zn-O (IAZO) TFTs with a homogeneous dual-active-layer structure are successfully fabricated at room temperature. The electrical properties including bias and illumination stabilities of the as-fabricated devices are investigated. The sputtered bilayer IAZO films are firstly prepared on SiO2/p+-Si substrates with different bottom (low-oxygen)/top (high-oxygen) layer thicknesses. When the thicknesses of the bottom/top layers are 20/10 nm, IAZO TFT exhibits the best overall performance and highest negative-bias-illumination stability, including a high saturation-mobility (12.05 cm2 V−1 s−1) and a small threshold-voltage-shift (−0.73 V). Then, in order to reduce the operating-voltage and meet the requirements of low temperature fabrication for flexible IAZO TFTs, a 70-nm-thick room-temperature-sputtered Ta2O5 film is employed to be the gate insulator. The performance of IAZO TFTs with Ta2O5 is greatly improved, especially the saturation-mobility (19.56 cm2 V−1 s−1) and subthreshold-swing (81 mVdec−1). They also exhibit outstanding bias and illumination stabilities as compared to the IAZO TFTs using SiO2. The largest threshold-voltage-shifts under positive-bias-illumination (5 V) and laser-illumination (450 nm) stresses are only − 0.78 and 0.05 V, respectively.

A Low-Power Memory-in-Pixel Circuit for Liquid Crystal Displays Comprising Low-Temperature Poly-Silicon and Oxide Thin-Film Transistors

In this paper, a new pixel structure using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for low-power liquid crystal displays (LCDs) is proposed. The extremely low off-state current of oxide semiconductor TFTs enables the proposed circuit to operate at a very low frame frequency of 1/60 Hz, so that the power consumption can be significantly reduced. In addition, the low-temperature polycrystalline silicon TFTs with high reliability directly drive pixels, which can achieve stable and flicker-free LCDs. The proposed circuit is fabricated using the LTPO TFT backplane and successfully verified by simulation and measurement results. The measurement results prove that the proposed circuit operates well without further programming for 60 s, and the power consumption in the panel (except backlight power) can be reduced to 0.02% of that of conventional LCD.

Causes of the Difference Between Hall Mobility and Field-Effect Mobility for p-Type RF Sputtered Cu₂O Thin-Film Transistors

The high Hall hole mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hall</sub> ) of cuprous oxide (Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O) has caused great interest in using this semiconductor for p-type devices in a future complementary metal-oxide-semiconductor (CMOS) thin-film transistor (TFT) technology. However, in most studies, the field-effect mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> ) achieved was reported to be much lower than μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hall</sub> . To understand the large gap between μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hall</sub> and μFE, in this work, we correlate RF sputtered p-type copper oxide (CuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) material properties with electrical characteristics by varying the film thickness. After vacuum annealing, the different thicknesses cause differences in the oxidation state and phase. Our results show that films with a higher Cu(I) fraction that form in the Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O phase give better TFT performance than CuO films. Nonetheless, the TFTs still exhibit a much lower μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> of 0.005-0.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s than the measured μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Hall</sub> value of 12.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V-s. We explore the reasons for this mobility gap by conducting contact resistance (RC) and interface trap (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) analysis. We find that the mobility difference can be minimized by reducing the high contact resistance (~33% of the total resistance in the ON-state) and high density of interface traps (~3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ).

Lowering the Trap-State Density of Transparent Amorphous Oxide Semiconductor-Based Thin Film Transistors Through Microwave Irradiation.

In this study, a low-thermal-budget microwave irradiation (MWI) technique was applied as a post-deposition annealing (PDA) process to lower the trap densities that exist in transparent amorphous oxide semiconductor thin film transistors (TAOS TFTs). As channel layers of TAOS TFTs, two types of indium gallium zinc oxide (IGZO) with different compositions as well as aluminum zinc tin oxide (AZTO) and zinc oxide (ZnO) thin films were deposited with various thicknesses through radio frequency (RF) magnetron sputtering at 25°C. Cost-effective and energy-efficient MWI was conducted to enhance the electrical performance of transistors by removing traps and defects. The electrical characteristics of IGZO (1:1:1 and 4:2:3)-, ZnO-, and AZTO-based TFTs treated by MWI were evaluated by measuring the transfer curves. In particular, the relation between the interface trap density (Dit) and bulk trap density (Nt) of microwave-irradiated TFTs was quantitatively evaluated by the subthreshold swing (SS) variation based on channel thickness. The results indicated that of the four types of channel layers, the performance of IGZO (4:2:3) TFTs was the best and that of AZTO TFTs was the worst, in terms of electrical properties such as on/off current ratio, mobility SS, and trap density. In particular, it was demonstrated that the trap density of MWI-treated TAOS TFTs was much lower than that of conventional furnace annealing (CFA)-treated devices. Despite the short annealing duration of a few minutes, the MWI more effectively reduced the trap sites than did the furnace treatment, and significantly enhanced the electrical properties of the TAOS TFTs. It is expected that high-performance TAOS TFTs can be fabricated by applying MWI, which is a highly efficient and low-thermal-budget annealing method, to the PDA process and can thus reduce trap density.

Investigation of electrical performance and operation stability of RF-sputtered InSnZnO thin film transistors by oxygen-ambient rapid thermal annealing

We investigated the electrical properties and operational stability of amorphous indium-tin-zinc-oxide (a-ITZO) thin-film transistors (TFTs). We fabricated the a-ITZO TFTs using deposition by radio frequency sputtering at room temperature followed by a rapid thermal annealing (RTA) process at different temperatures and oxygen pressure (P O2). This is a more practical annealing route compared to a conventional furnace. Based on film densification and oxygen vacancy optimization, the a-ITZO TFTs exhibited 9.8 cm2 Vs−1, 0.82 V/decade and 1.39 V, for saturation mobility, sub-threshold swing and threshold voltage, respectively. Operation stability tests and hysteresis behavior of a-ITZO TFTs suggest that oxygen vacancy concentration of a-ITZO thin films gradually decreases under higher P O2, consequently affecting the threshold voltage and the shift seen after a gate bias stress test. This observation suggests that gate bias stress and hysteresis stability of an a-ITZO device is due to the effect of oxygen-controlled pressure in the RTA process. This a-ITZO TFTs electrical characterization qualitatively coincides with x-ray photoelectron spectroscopic analyses of oxygen vacancy concentration in a-ITZO thin films. Thus, our systematic a-ITZO thin film optimization using the oxygen-ambient RTA process is a practical basis for high-performance amorphous oxide semiconductor TFT post-annealing methods.

Extraction Technique for Flat Band Voltage Using Multi-Frequency C – V Characteristics in Amorphous InGaZnO Thin-Film-Transistors

An extraction technique for flat band voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ) in an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) using the frequency-independent C - V relationship which is taken from the measured multi-frequency C - V characteristics, is proposed. The proposed method comprises the consideration of multiple physical parameters for accurate VFB extraction, including the sub-gap density of states, doping concentration, gate oxide capacitance, and series resistance. The method was verified by comparing both the measured current-voltage characteristics and the extracted V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> value with the technology computer-aided design simulation results. Moreover, we confirmed the versatility of the method by extracting VFB from devices with different oxygen contents. The proposed physical-based technique showed better accuracy and compatibility with amorphous oxide semiconductor (AOS) TFTs compared with classical empirically based methods. We believe that our technique is useful for the experimental design and optimization of the gate metal-dielectric-AOS stack for highperformance AOS TFTs.

(Invited) Device Scalability of InGaZnO TFTs for Next-Generation Displays

Amorphous oxide semiconductor thin-film transistors (TFTs) are used as the backplane for large-screen, high-resolution OLED and LCD displays. Amorphous InGaZnO (a-IGZO) TFTs are widely used in commercialized TVs, tablets, and wearable displays for its good device performance, stability, and process controllability. Also, due to its extremely low off-current, a-IGZO TFTs are used for low refresh rate and low-power displays. Furthermore, a-IGZO TFTs have a low process temperature, enabling fabrication on various substrates (including flexible films), and also hybrid integration with other backplane technologies, such as LTPS or Si CMOS. By taking advantage of the low off-current and low process temperature, a-IGZO can be monolithically integrated in the back-end of Si CMOS for low-power applications, as well as embedded memories for long retention and non-volatile operation. There are many incentives to shorten the channel length of IGZO TFTs. First, shorter channels can boost the current without incorporating high-mobility oxides, which usually suffer from reliability issues and small process margin. When gate drivers are integrated directly onto the panel, larger currents allow smaller device footprint, thinner bezel width, and less dead space. Second, transistors with sub-micron pitch are desired to bridge the pixel gap between smartphone displays and micro-displays, and to be used for consumer AR/VR displays with > 1000 ppi. Third, reduced device length is necessary for fine-grained integration with nanoscale CMOS. However, short-channel TFTs suffer from short-channel effects (SCE). For example, threshold voltage (Vt) roll-off, where the Vt reduces for short channel lengths, causes device variability and hence, worse process tolerance. Therefore understanding and control of SCE is critical for designing and fabricating short-channel TFTs.In this paper, we study the device scalability of short-channel IGZO TFTs down to 1μm. The electrical channel length (Leff) is not the same as the gate length (Lg), and is determined by the carrier profile at the gate edges. Leff ( = Lg - ΔL) is obtained by the transmission line method (TLM), or shift-and-ratio method. Accurate ΔL extraction is important in determining the exact device mobility. Since scalability is related to the carrier concentration profile, it is strongly dependent on the process, where oxygen and hydrogen content varies with process conditions, and profiles change during thermal treatments. Devices with higher carrier concentration generally result in larger ΔL and worse SCE. Device simulations using TCAD shows the dependence on overlap (Lov), slope of carrier Gaussian decay (Xc), channel carrier concentration (Nch) on the Leff and SCE. TCAD simulation results are matched with experimental measurements for verification of the simulation models and parameters used. We define a critical carrier concentration (Ncrit) which defines the Leff. Changing the carrier profile while maintaining Ncrit results in little difference in ΔL. For devices with an underlap, similar ΔL values result in similar SCE. However, for devices with an overlap, even with the similar ΔL values, SCE is more sensitive to carrier profile at the channel edges. This study shows that SCE may be controlled through shaping of the carrier concentration profile through optimization of the device structure and process conditions allowing fabrication of short-channel TFTs with good scalability.