Packaged Semiconductor Devices Research Articles

Numerical simulation of copper electrodeposition for Through Silicon Via (TSV) with SPS-PEG-Cl additive system

Through silicon via (TSV) technology is crucial for modern semiconductor device package, enabling high-performance integrated microsystems. This paper investigates the mechanism of the bottom-up copper deposition process in TSV, leveraging a co-adsorbed polyether-Cl-suppression layer and accelerators for optimized filling profiles. We present numerical simulations of the effects of additives (accelerator, suppressor) and chloride ions (Cl−) on the TSV filling. By varying the substance concentration, we obtain three distinct filling models, including filling with voids, conformal filling and bottom-up filling. We analyzed the distribution of various substances and current densities to elucidate the filling mechanism. Furthermore, TSV filling experiments were conducted, and the simulated profiles were in good match with the filling experiments. It is verified that the feasibility of the proposed numerical model by generalizing to 90μm × 180 μm, 50μm × 100 μm, and 10μm × 100 μm via holes of different sizes and aspect ratios.

Cu TSV Filling with Cetyltrimethyl Ammonium Cations (CTA+) and Br-

Through silicon via (TSV) technology is essential for the three-dimensional packaging of electronic devices. After creating high-aspect-ratio vias, Cu electrodeposition is performed to achieve defect-free Cu interconnection. The most important purpose of electrodeposition process is to fill the features without any defects, and this process is called superfilling, superconformal deposition, or bottom-up filling. Since TSV is a key component for the packaging of semiconductor devices, various research on the electrodeposition process for TSV filling have been studied. Defect-free TSV filling can be achieved by introducing appropriate organic/inorganic additives into the electrolyte and the filling performance can be promoted by pulse reverse electrodeposition.1-3 Generally, it has been reported that Cu bottom-up filling at TSVs can be obtained by three-additive combinations (suppressor, accelerator, and leveler) or by using a single suppressor. Tetronic 701 is the most representative suppressor in a single-additive filling method, which was based on S-shaped negative differential resistance (S-NDR) behavior.4-6 In the case of three-additive systems, various levelers that contained ammonium functional groups, a polymeric suppressor, and an accelerator have been researched.7,8 Furthermore, it has been reported that halide ions (Br- and I-) can act as levelers for inducing Cu bottom-up filling at TSVs.9,10 This study investigated the effects of cetyltrimethyl ammonium cation (CTA+) and halide ion on TSV filling in the presence of an accelerator and polymeric suppressor. The influences of two halide ions, Cl- and Br-, on the adsorption of CTA+ and their convection dependency were studied. This presentation will introduce the electrochemical behaviors of halide ions and CTA+ and defect-free filling using the optimum combination of these additives. References M. Hayase, and K. Otsubo. "Copper deep via filling with selective accelerator deactivation by a reverse pulse" J. Electrochem. Soc.,157, D628 (2010).Q.S. Zhu, X. Zhang, C.Z. Liu, and H.Y. Liu. "Effect of reverse pulse on additives adsorption and copper filling for through silicon via" J. Electrochem. Soc.,166, D3006 (2019)Q.S. Zhu, A. Toda, Y. Zhang, T. Itoh, and R. Maeda. "Void-free copper filling of through silicon via by periodic pulse reverse electrodeposition" J. Electrochem. Soc.,161, D263 (2014)T. P. Moffat, and D. Josell. "Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns" J. Electrochem. Soc.,159, D208 (2012)D. Joell, and T. P. Moffat. "Superconformal copper deposition in through silicon vias by suppression-breakdown." J. Electrochem. Soc.,165, D23 (2018)M. Dong, Y. Zhang, T. Hang, and M. Li. "Structural effect of inhibitors on adsorption and desorption behaviors during copper electroplating for through-silicon vias." Electrochim Acta372 (2021)M. J. Kim, Y. Seo, J. H. Oh, Y. Lee, H. C. Kim, Y. G. Kim, and J. J. Kim. "Communication—halide ions in teg-based levelers affecting TSV filling performance." J. Electrochem. Soc.,163, D185 (2016)V. Q. Dinh, K. Kondo, V. H. Hoang, and T. Hirato. "Communication—Bottom-up TSV filling using sulfonated diallyl dimethyl ammonium bromide copolymer as a leveler." J. Electrochem. Soc.,166, D505 (2019)M. J. Kim, H. C. Kim, and J. J. Kim. "The influences of iodide ion on Cu electrodeposition and TSV filling." J. Electrochem. Soc.,163, D434 (2016)M. Sung, Y. Yoon, J. Hong, M. J. Kim, and J. J. Kim. "Bromide ion as a leveler for high-speed TSV filling." J. Electrochem. Soc., 166, D546 (2019) Figure 1

Technological sustainable materials and enabling in semiconductor memory industry: A review

This paper provides an overview of current and future deployment of recyclable direct materials and sustainable materials through recycling of interconnect metals used in semiconductor assembly and packaging. Also, with the aim to study the key technical barriers, challenges of deployment and its reliability performance of impacts of sustainable materials used in semiconductor device packaging, this paper lays out the importance of noble metals and polymeric materials in terms of its materials sustainability for the next decade. This article briefly reviews key aspects of recycled materials reliability concerns, deployment of recycled gold (Au) wire, recycled copper (Cu), and other noble metals in semiconductor packaging and assembly. Frontend chip fabrication sustainability issues and their corresponding countermeasures are covered in this review article as well.

A fundamental study of improving thermal interface connection by using silane modified, in-situ formed silver-graphene fillers in epoxy polymers for future semiconductor device packaging

Over the past half-century, the increase of on-chip power and on-chip integration density has created new thermal management challenges for 2.5D/3D semiconductor packaging. High-performance thermal management materials in electronic encapsulation are very important to ensure the performance and reliability of the electronic devices. Graphene-based polymer composites have attracted much attention due to the ultrahigh thermal conductivity and large surface area of graphene. However, graphene nanosheets easily aggregate and lack functional groups on their surfaces, leading to phonon scattering within the interfaces. In this work, silver nanoparticles are in-situ formed on the graphene surface by a facile method, then the graphene-silver nanofillers are modified by (3-Mercaptopropyl)trimethoxysilane (MPTS). MPTS reacts with silver nanoparticles to connect them with epoxy. Also, silver nanoparticles on the surface of graphene can fuse together to form metallurgical joints that connect graphene nanosheets.With the fundamental understanding of sintering mechanisms and reducing two types of thermal interfacial resistances (filler-filler and filler-epoxy interface resistances) simultaneously, the resultant epoxy nanocomposites achieve a high through-plane thermal conductivity of 0.99 W/mK at 8 wt% loading. This corresponds to a 465.7% increase in thermal conductivity as compared to that of neat epoxy. Also, the nanocomposites present a low CTE and high thermal stability. They show strong cooling capability and heat dissipation as thermal interface materials (TIMs) through both experimentation and simulation, providing a promising new insight into thermal management materials to meet the demands of next generation high-power and high-density semiconductor packaging.

Humidity effect on electrical performance and bias stability of solution-processed In2O3 thin film transistor

ABSTRACT Relative humidity (RH) in storage environment has a great impact on the electrical performance of thin film transistors (TFTs), and the RH is critical for semiconductor manufacturing and device packaging. In this work, solution-processed indium oxide (In2O3) TFT is fabricated, and the electrical performance of the device is investigated after being exposed to various RH conditions. It is found that the threshold voltage (Vth) and the mobility of In2O3 TFT exhibit clear responses to the RH ranging from 23% to 85%. The inherent mechanism about the humidity effect on the electrical performance is elaborated, and this is due to the “donor effect” from the absorbed water molecules. In addition to the effect on Vth and mobility, RH also exhibits a significant effect on the electrical stability of the TFT. The experimental result indicates that the In2O3 TFT exposed to RH <50% exhibits excellent stability with an applied positive bias stressing for 2000s.

X-ray imaging of silicon die within fully packaged semiconductor devices

X-ray diffraction imaging (XRDI) (topography) measurements of silicon die warpage within fully packaged commercial quad-flat no-lead devices are described. Using synchrotron radiation, it has been shown that the tilt of the lattice planes in the Analog Devices AD9253 die initially falls, but after 100 °C, it rises again. The twist across the die wafer falls linearly with an increase in temperature. At 200 °C, the tilt varies approximately linearly with position, that is, displacement varies quadratically along the die. The warpage is approximately reversible on cooling, suggesting that it has a simple paraboloidal form prior to encapsulation; the complex tilt and twisting result from the polymer setting process. Feasibility studies are reported, which demonstrate that a divergent beam and quasi-monochromatic radiation from a sealed X-ray tube can be used to perform warpage measurements by XRDI in the laboratory. Existing tools have limitations because of the geometry of the X-ray optics, resulting in applicability only to simple warpage structures. The necessary modifications required for use in situations of complex warpage, for example, in multiple die interconnected packages are specified.

Doping low-cost SiOx (1.2

As a die-attach material, nano-Ag paste is extensively applied in the packaging of power semiconductor devices. However, silver is highly prone to migration, particularly at high temperatures. In this paper, we studied the inhibition effect of doping different proportions (0.1% and 0.2%) of low-cost SiOx (1.2 < x < 1.6) nanoparticles (NPs) instead of noble metals to nano-Ag paste on the electrochemical migration (ECM) of silver at high temperatures. The ECM tests showed that silver migration was significantly postponed by the doping of SiOx NPs and the lifetime of sintered Ag-0.2%SiOx was ∼2.6 times than that of sintered Ag at 400 °C and 200 V. The great news was that the mechanical, thermal as well as electrical performances were almost not impacted by the doped SiOx NPs. The mechanism of inhibiting silver migration by doping SiOx NPs was proposed as that the oxidation of SiOx hindered the oxidation of silver. Then a lifetime model was determined to predict the failure of both the sintered nano-Ag and the sintered Ag-SiOx at high temperatures to provide theoretical guidance for the reliability design of the high temperature package of power semiconductor devices.

Optimization of Semiconductor Device Packaging Singulation Process

With the advancement of semiconductor technology, the assembly process of semiconductor packaging is driving the devices to become smaller and smaller in size. One of the critical processes in backend assembly is the product’s singulation to separate bulk processed products into individual unit. Before the sawing process kick-off, saw blade preparation (blade dressing) has to be performed. Blade dressing is the process of sharpening the saw blade surface to expose the diamond grits to the blade surface that are covered by the blade bonding material (Nickel-based). Inappropriate blade preparation technique induces burn mark defect to semiconductor devices. This research presented the dressing process optimization on critical factors using Silicon carbide (SiC) as part of the effort to enhance the product quality. The 2k Full Factorial Design of Experiment (DOE) methodology, with consideration of three factors namely Blade Revolution Per Minute (RPM), Feedspeed and Dress Pass. The overall singulation process yields performance improvement by reducing the burn mark to < 0.1% with optimum saw blade preparation technique. Besides, the optimized process complementarily contributes to less kerf deformation and dressing wear.

Characterization Method of Joints for Power Semiconductor Device Packaging

Characterization Method of Joints for Power Semiconductor Device Packaging

Optimization of pick-and-place in die attach process using a genetic algorithm

The entire semiconductor manufacturing process can be largely divided into two sequential sub-processes that are commonly referred to as front-end and back-end production. Both production processes involve many complicated and elaborate steps for wafer fabrication, probe testing and sorting, assembly, final test, etc. The front-end process refers to wafer fabrication process, whereas the back-end process refers to the assembly, packaging, and testing of individual semiconductor devices. Once the front-end process is complete, the wafers are transferred to the back-end process in order to facilitate its integration into electronic devices and to take final performance test. In back-end production process, based on quality and location information of individual chip (die) derived from the EDS process, only good semiconductor chips (dies) are individually picked up by an automatic robot arm and then attached to the support structure (e.g., the lead frame) on a strip. This process is called die attach process. In order to improve the production efficiency of die attach process, it is necessary to evaluate various robot arm operation methods (rules) and then to provide the most efficient operation method since the total transfer distance (or total transfer time) considerably depends on the robot arm operation methods as well as the distribution of good chips on wafers. Thus, in this research, a pick-and-place problem of the die attach process is mathematically formulated and several transfer methods are compared.

Effects of self-aligned electroplating Cu pillar/Sn-xAg bump on dense Al lines for chip-to-package connection

Self-aligned electroplating is applied to form the Cu pillar/Sn-Ag bump for semiconductor device packaging, while passivation SiN cracks are usually observed at the bump edge on the bump of the array (BOA). In this paper, the simulation method was used to investigate the mechanism of SiN cracks and then, the bump process was optimized to improve the mechanical properties of the Cu pillar/Sn-Ag bump. It was found that higher reflow rounds could improve the shear strength due to the large degree of contact between the rugged scallop-like shape of the Cu6Sn5 and the Sn-Ag solder. The fracture plane cleaved between the Sn-Ag and Cu6Sn5 interface is consistent with the simulation results. The hardness of the Sn‒Ag solder is proportional to the reflow rounds, and the amount of Ag3Sn phase precipitation within the Sn-Ag solder contributes to the hardness value. In contrast, the disadvantage is that thermal residual stress could deteriorate the SiN crack, especially for a BOA structure The study concludes that an optimal bump process, including Sn-2%Ag solders at 260°C for 30s, could obtain a high shear strength and appropriate solder hardness without passivated SiN cracking.

Metallic TIM Testing and Selection for Harsh Environment Applications for GaN RF Semiconductors

Summary An important determinant of device reliability is operating temperature control. Maintaining a semiconductor device at or below the maximum rated junction temperature (Tj) is accomplished through careful thermal management design and selection of well-performing thermal interface materials (TIM) that minimize efficiency losses in packaging and between the semiconductor device package and a heat sink or liquid cold plate. Thermal management design is increasingly important in harsh operating environments, especially where higher operating temperatures are specified. Minimizing thermal resistances through each semiconductor package material stack and at the external case or package surface of the device are important aspects of maintaining operating temperatures within specified maximum values. In addition, certain semiconductor devices require an electrical path from the semiconductor case to an external component. Maximizing electrical performance of gallium nitride (GaN) RF semiconductors is critical to system performance, as a primary example. The on-going transition within RF and microwave systems from silicon to GaN devices has increased the need for thermal interface materials which offer both improved thermal performance and electrical conductivity. Additionally, GaN semiconductor die are typically smaller in footprint and, even with equivalent power dissipation values, therefore may operate with higher heat flux values that require greater attention to proper thermal solution design. To address such needs, recently-developed forms of metallic TIM preforms are available for integrated circuits, power semiconductors, and RF devices. Understanding how these materials may be tested and selected for specific application requirements is the subject of this discussion.

Reliability Characterization of Au–In Transient Liquid Phase Bonding Through Electrical Resistivity Measurement

Transient liquid phase (TLP) die-attach bonding is an attractive technique for high-temperature semiconductor device packaging. In this paper, the material reliability of gold–indium (Au–In) TLP bonding is investigated utilizing electrical resistivity measurement as an indicator of material diffusion. Samples were fabricated featuring a TLP reaction, representative of TLP die-attach, by depositing TLP materials on glass substrates with various Au–In compositions, but with identical barrier layers, and were then used for reliability investigation. The samples were annealed at 200 °C and then stressed with thermal cycling. Samples containing high indium content in the TLP bond are shown to have poor reliability due to material diffusion through barrier layers, whereas the samples containing sufficient gold content proved reliable through electrical resistivity measurement, energy-dispersive X-ray spectroscopy, focused ion beam, and scanning electron microscope characterization.

ワイドバンドギャップ半導体によるパワーデバイスの性能改善と課題

Wide-bandgap semiconductors such as SiC have been studied eagerly as a next generation power devices because of its superior physical property. Though very high carrier density is main reason for superior characteristics of that, there are some problems to realize the predicted performance. One is heat radiation limited by package performance. The other is SCSOA (Short Circuit Safe Operating Area) limited by heat capacity of power device itself. Besides, parasitic inductance of power circuitry affects switching losses and switching speed. High current density operation is the key role to realize the predicted performance, and with that purpose, semiconductor device technology, package technology, and circuit technology must be optimized as the total engineering.

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.

Low cost packaging for gas sensors

MEMS technologies have enabled the development of various sensors including gas sensors in a miniaturized and cost effective way. Sensor systems are being developed using these sensor chips where chip packaging is still a major cost due to special requirements. This paper focuses on the packaging needs of a MEMS based gas sensor. These gas sensors have various applications in safety systems for fire and harmful gases detectors for automobiles, home, offices, factories, environment, etc. A low cost packaging solution for MEMS based gas sensors is elaborated which is suitable for the trace level detection of various lethal gases like H2S, PH3, CO, CO2, NH3 etc. To enable the vast and multiple applications of these gas sensors it is important to provide a low cost sensor system which is low power and can be operated on battery. Standard semiconductor device packages like TO headers are costly and not suitable for low cost devices. Proposed packaging scheme uses printed circuit board (PCB) as substrate material (FR4) where reliable low resistance (1---2 ohm) interconnects are provided by conducting epoxy. PCB based packages add very little extra power (3---5 mW) to the power required for micro-heater that heats gas sensor film up to 300 °C. Packaged gas sensors were tested for their reliability in two different conditions i.e. 1 h ON reliability test and repetitive ON/OFF (100 times) test. These packages have additional advantages of being more mechanically stable than wire bonded packages and easy processing in comparison to Transistor Outline (TO) headers. Infrared imaging of the packaged device in forced condition shows the stability of the package.

Proposed Solution to the Problem of Thermal Stress Induced Failures in Medical Electronic Systems

The concept of miniaturization has propagated to all types of electronic applications. The complexity of electronic systems has been increasing due to increase in the number of functions and features offered to the users. At the same time the number of devices working per unit volume of the system has increased enormously, due to which the power density per unit volume has increased. Dissipating high power in small volumes has increased the thermal problems in all types of electronic systems, including medical gadgets. Thermal stress has been identified to be the major cause of failure of electronic devices in electronic systems, based on the analysis of failures, based on research work. The causative mechanism of failure of semiconductor device package due to thermal overstress in medical electronic systems is the differential expansion between plastic and metal parts of the device which causes a differential strain and package failure. Selection of materials with similar coefficient of thermal expansion is important to prevent thermal overstress caused failures. In this paper, we discuss a technique which uses mathematical analysis to provide a solution to this problem of selecting the suitable material to prevent differential thermal stress failures in medical electronics systems.

Back side SIMS analysis

Depth profiling SIMS analysis to determine diffusion of an element from a surface layer into a substrate or penetration of a species through a barrier layer can be very difficult to achieve because one cannot readily detect a trace amount of an element after depth profiling through a matrix level of the same element. Removal of the substrate and analysis from the back of the sample has provided a solution to this problem. Substrate removal methods have been either mechanical polish followed by a chemical etch or mechanical polish alone. The latter method has provided successful results for a wide range of studies including penetration of Cu though a barrier material, diffusion from high‐k dielectric layers, and site specific analysis on a product wafer. In order to make the polishing method more routine and reduce the time required, substrate removal was investigated with use of a milling machine designed to de‐process packaged semiconductor devices. Initial work on an Si substrate shows residual Si less than 100 nm could be obtained in a region that was subsequently analyzed with good depth resolution in a SIMS depth profile. Mesa sample preparation with this instrument was also demonstrated. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Spectral reflectometry for metrology of three-dimensional through-silicon vias

The technology for semiconductor device packaging is rapidly advancing in response to increasing demand for smaller and thinner electronic devices. Three-dimensional chip stacking that uses through-silicon vias (TSVs) is a key area of technical focus, and the high-density TSV (HDTSV) is a major enabler of three-dimensional (3-D) integrated circuit technology. The ongoing development of this novel technology has created a need for noncontact characterization. One of the main challenges for 3-D TSV metrology is measuring high aspect ratio features that limit conventional optical microscopy techniques. We demonstrate the use and enhancement of an existing wafer metrology tool, a spectral reflectometer, by developing and implementing theoretical models and measurement algorithms for inspection of HDTSVs. It is capable of measuring the depth of vias, and can also be used for the estimation of bottom roughness and bottom shapes of vias through the model fitting. Our nondestructive solution has measured TSV diameters as small as 3 μm and aspect ratios >16.5∶1 . Submicron depth measurement accuracy has been verified in the range of 30 to 60 μm on via depth. Metrology results from actual wafers formed from 3-D interconnect processing are presented.

Superior performance and reliability of copper wire ball bonding in laminate substrate based ball grid array

PurposeThe purpose of this paper is to provide a systematic method to perform long‐term reliability assessment of gold (Au) and copper (Cu) ball bonds in fineline ball grid array package. Also with the aim to study the apparent activation energies (Eaa) and its associated wearout mechanisms of both Au and Cu wire in semiconductor device packaging. This paper discusses the influence of wire type on the long‐term reliability and mechanical performance after several component reliability stress tests.Design/methodology/approachA fineline ball grid array (FBGA) package with Cu and Au wire bonds was assembled with green molding compound and substrate. Samples are subjected for long‐term high temperature storage bake test at elevated temperatures of 150°C, 175°C and 200°C. Long‐term reliability plots (lognormal plots) are established and Eaa of both ball bonds are determined from Arrhenius plots. Detailed failure analysis has been conducted on failed sample and HTSL failure mechanisms have been proposed.FindingsReliability results show Au ball bond in FBGA package is observed with higher hour‐to‐failure compared to Cu ball bonds. The Eaa value of high temperature storage life (HTSL) reliability for Au ball bond is lower than Cu ball bond. Typical HTSL failure mechanism of Au ball bond is induced by micro‐voiding and AuAl intermetallic compound (IMC) micro‐cracks while CuAl IMC micro‐cracking (induced by Cl− corrosion attack and micro‐cracking) caused wearout opens in Cu ball bond. These test results affirm the test‐to‐failure data collected is a useful method for lifetime prediction and Eaa calculation.Practical implicationsThe paper reveals higher reliability performance of Cu ball bond in FBGA flash memory package which can be deployed in flash memory FBGA packaging with optimised package bill of materials.Originality/valueThe test‐to‐failure methodology is a useful technique for wearout reliability prediction and Eaa calculation.