Abstract
The technology for semiconductor device packaging is rapidly advancing in response to increasing demand for smaller and thinner electronic devices. Three-dimensional chip stacking that uses through-silicon vias (TSVs) is a key area of technical focus, and the high-density TSV (HDTSV) is a major enabler of three-dimensional (3-D) integrated circuit technology. The ongoing development of this novel technology has created a need for noncontact characterization. One of the main challenges for 3-D TSV metrology is measuring high aspect ratio features that limit conventional optical microscopy techniques. We demonstrate the use and enhancement of an existing wafer metrology tool, a spectral reflectometer, by developing and implementing theoretical models and measurement algorithms for inspection of HDTSVs. It is capable of measuring the depth of vias, and can also be used for the estimation of bottom roughness and bottom shapes of vias through the model fitting. Our nondestructive solution has measured TSV diameters as small as 3 μm and aspect ratios >16.5∶1 . Submicron depth measurement accuracy has been verified in the range of 30 to 60 μm on via depth. Metrology results from actual wafers formed from 3-D interconnect processing are presented.
Highlights
The 2011 International Technology Roadmap for Semiconductors expanded on the requirements for metrology of three-dimensional (3-D) interconnects to include wafer alignment, interface bonding, and through-silicon vias (TSVs).[1]
Six of TSV arrays with circular openings, nominal critical dimension (CD) values of 5, 10, 15, 20, 25, and 30 μm and varying etched depths patterned on each die across a 200-mm wafer
The cross-sectional scanning electron microscope (SEM) images shown in Figs. 4(b) and 4(c) are a wide range view and a bottom close-up view, respectively, which were used for a measurement comparison after the spectral reflectometry experiments
Summary
The 2011 International Technology Roadmap for Semiconductors expanded on the requirements for metrology of three-dimensional (3-D) interconnects to include wafer alignment, interface bonding, and through-silicon vias (TSVs).[1]. One example uses a scanning white-light interferometer with a small imaging aperture and low NA illumination to scan the objective perpendicular to the surface to generate signals for in-line TSV depth measurement.[6] the. Another example uses a backside infrared interferometric technique for sensing the thickness of a wafer for HAR vias 1 and 5 μm in size; there is no sidewall interference to inhibit optical techniques, and the infrared sensor’s accuracy and repeatability are independent of the aspect ratio of the via.[7] the illumination spot size (either 15 or 5 μm) limits the transverse resolution. The potential for verifying the accuracy of measurements of the via depth with crosssection SEM will be discussed
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