Semiconductor Circuits Research Articles

New SiC Kicker Power Supply for J-PARC

A new kicker power supply using silicon carbide metal–oxide semiconductor field-effect transistors (SiC-MOSFETs) is under development at the Japan Proton Accelerator Research Complex (J-PARC). SiC-MOSFETs fabricate compact high-speed pulse power supplies to replace the thyratron switch power supply. The base circuit of the new power supply uses the linear transformer driver (LTD) system, and the semi-conductor module circuit comprises a radial symmetry type that achieves low noise. The three main components of the current kicker power supply, i.e., the thyratron, pulse-forming network (PFN) circuit, and end clipper, can be assembled on a single board as the new module circuit board. The new power supply contains a 1.25 kV/2 kA main board that forms a trapezoidal pulse and a 0.1 kV/2 kA correction board, compensating for the flat section droop. The 32 main boards and 20 correction boards are hierarchically connected in series to achieve the waveform specifications required for the J-PARC rapid cycling synchrotron (RCS) kicker power supply: output voltage of 40 kV, output current of 2 kA, and pulse width of 1.2 μs. Furthermore, a 25 % power saving has been confirmed and an insulating cylinder for the conductor has been developed to suppress corona discharge and withstand continuous operation for a long time.

Hierarchies in Visual Pathway: Functions and Inspired Artificial Vision.

The development of artificial intelligence has posed a challenge to machine vision based on conventional complementary metal-oxide semiconductor (CMOS) circuits owing to its high latency and inefficient power consumption originating from the data shuffling between memory and computation units. Gaining more insights into the function of every part of the visual pathway for visual perception can bring the capabilities of machine vision in terms of robustness and generality. Hardware acceleration of more energy-efficient and biorealistic artificial vision highly necessitates neuromorphic devices and circuits that are able to mimic the function of each part of the visual pathway. In this paper, wereview the structure and function of the entire class of visual neurons from the retina to the primate visual cortex within reach (Chapter 2) are reviewed. Based on the extraction of biological principles, the recent hardware-implemented visual neurons located in different parts of the visual pathway are discussed in detail in Chapters 3 and 4. Furthermore, valuable applications of inspired artificial vision in different scenarios (Chapter 5) are provided. The functional description of the visual pathway and its inspired neuromorphic devices/circuits are expected to provide valuable insights for the design of next-generation artificial visual perception systems.

The Development of a Compact Pulsed Power Supply with Semiconductor Series Connection

In this study, high-voltage switching was performed by connecting semiconductors in series. By employing Snubber circuits and voltage divider resistors for each semiconductor, the destruction of the semiconductors was prevented. Additionally, a pulse transformer was installed between the function generator and the photocoupler to isolate the gate circuit, preventing electrical discharges in the circuit and enabling operation at an output voltage of 10 kV and an operating frequency of 200 Hz. The temperature of the semiconductors increased with the increase in operating frequency, which was counteracted by connecting charging resistors and capacitors to limit the current to the semiconductors. As a result, operation at 430 Hz became possible. Furthermore, a saturable inductor (SI) was connected to enable continuous operation. The SI delays the rise of the current and creates a phase difference, thereby reducing the power consumption of the conductor and mitigating the temperature rise, enabling continuous operation at 300 Hz. Moreover, by increasing the number of semiconductor series stages to six, an output voltage of 20 kV was confirmed in tests. By using two semiconductor series circuits, the pulsed power supply that can be changed to any pulse width was also created. As a result, output voltages with arbitrary pulse widths from 5 μs to 30 μs were confirmed.

Kinetic and in Situ Analysis for Ion Transport Process in Copper Electrodeposition Using Polyelectrolyte Membranes

Electrodeposition of metals has been one of the most important techniques for fabrication of microelectronics and semiconductor elements in printed circuit boards and electronics device manufacturing. From the industrial perspective, the management of electrodeposition bath is crucial to maintain product quality, productivity and long-term stability of the bath, the subject of which includes bath temperature, concentration of metal salts, supporting electrolytes, and various additives. Although these parameters have been optimized to achieve desirable deposition rate, depending on the product type and morphology, some environmental issues regarding with generating mist, sludges, and waste effluent during electrodeposition process are becoming apparent. Additionally, current electrodeposition process has been developed for substrates with large surface area and for large scale production of electronic components and could not be suitable for recent demand of small-lot, site-selective and multiproduct device microfabrication. Therefore, high-performance deposition system, allowing site-selective electrodeposition of metals without generation of large amount of effluents, needs to be developed to impact above environmental and cost perspectives. Recently, we reported a novel method for electrodeposition of metals using polyelectrolyte films attached on cathode substrate (solid electrodeposition: SED) [1]. The SED process enables one to deposit metals directly on the cathode surface from metal ions inside solid polyelectrolyte membranes and has desirable advantages including higher deposition rate, site-selectivity, and deposition using lower concentration electrolyte solution without additives. In this SED process, thin polyelectrolyte membrane sandwiched between electrodes effectively concentrates metal ions through interfacial penetration, which increases the conductance between the electrodes and realizes solid-state electrodeposition that produces no mist, sludge, or even waste effluent.In this study, we present mechanistic analysis of the SED process, including transport kinetics and equilibrium reaction of copper ions at solution/membrane interface (Figure A). We show that both detailed experimental results and theoretical calculations reveal that ion transfer in the present electrodeposition system is a penetration-controlled process at the solution/polyelectrolyte interface, providing an inherently different ion-transport mechanism compared to that of conventional diffusion-controlled electrodeposition. Several parameters including penetration rate constant, electrode geometry, and distance between polyelectrolyte and anode are varied to investigate the ion-transport process in the SED system. When the anode is slightly apart from polyelectrolyte film to introduce electrolyte layer but is closer as far as possible to it, greater current density for copper electrodeposition is achieved at steady state than that for the systemwhere the membrane is sandwiched by electrodes (Figure B). This can be due to maximum ion penetration rate and minimum resistivity of electrolyte layer, providing better deposition setup for high performance electrodeposition. Additionally, we also performed in situ analysis of concentration of copper ions inside polyelectrolyte film via visible absorption spectroscopy using a miscofiber during electrodeposition. As a result, concentration of copper in the polyelectrolyte film decreased initially and then became constant (steady state) as the deposition proceeded, a fashion of which was quite similar with that of current-time curves simultaneously acquired during constant-voltage electrodeposition.The developed deposition setup demonstrates stable electrodeposition of copper using aqueous copper sulfate solution with no supporting electrolytes and/or additives at deposition rate of few micrometers per minute. As a site-selective deposition tool, the SED process can be used to fabricate microelectronic and even semiconductor circuit elements in a manner that resembles stamping deposition, and is suitable for small-lot, on-demand, and multi-product microfabrication.Reference:[1] K. Akamatsu, S. Nakano, K. Kimura, Y. Takashima, T. Tsuruoka, H. Nawafune, Y. Sato, J. Murai, H. Yanagimoto, ACS Appl. Mater. Interfaces, 13 (2021) 13896-13906. Figure 1

Molecular Mechanism of Selective Al2O3 Atomic Layer Deposition on Self-Assembled Monolayers.

Area-selective atomic layer deposition (AS-ALD) of insulating metallic oxide layers could be a useful nanopatterning technique for making increasingly complex semiconductor circuits. Although the alkanethiol self-assembled monolayer (SAM) has been considered promising as an ALD inhibitor, the low inhibition efficiency of the SAM during ALD processes makes its wide application difficult. We investigated the deposition mechanism of Al2O3 on alkanethiol-SAMs using temperature-dependent vibrational sum-frequency-generation spectroscopy. We found that the thermally induced formation of gauche defects in the SAMs is the main causative factor deteriorating the inhibition efficiency. Here, we demonstrate that a discontinuously temperature-controlled ALD technique involving self-healing and dissipation of thermally induced stress on the structure of SAM substantially enhances the SAM's inhibition efficiency and enables us to achieve 60 ALD cycles (6.6 nm). We anticipate that the present experimental results on the ALD mechanism on the SAM surface and the proposed ALD method will provide clues to improve the efficiency of AS-ALD, a promising nanoscale patterning and manufacturing technique.

Brushless direct current motors with permanent magnets for marine electric drive systems: state and prospects

The main trends in the development of designs, power semiconductor circuits and control systems of promising valve electromechanical converters — brushless DC motors with permanent magnets for marine electric drive and automation equipment, are discussed in the paper. A variant of their implementation in an adjustable electric drive is presented. The object of the study is a brushless direct current electromechanical system, including a synchronous machine with magnetoelectric excitation, covered by positional feedback through a dependent controlled valve switch, and the subject is structures, the circuit of the power part, control systems, the algorithm of functioning and characteristics. The purpose of the research is to evaluate the operational features, properties and possibilities of introducing brushless direct current motors with permanent magnets as marine electric drive systems of low and medium power. The results of research and development are embodied in experimental industrial samples. A variant with microprocessor control has been developed for marine electric drive systems. The switch is assembled on transistor switches that provide high reliability and enhance the functionality of the control system. The minimum necessary system of logical variables, ensuring the implementation of rational laws of switching and speed control, has been formed. Operational characteristics at various leading angles of switching on the switch valves are presented. The presence of pole shoes at the poles introduces significant features in the patterns of their change. The main advantages and features of the proposed design and circuit solutions are formulated in the conclusions. It is indicated that valve motors with excitation from permanent magnets are the most promising solution in terms of integrating an electromechanical converter into an adjustable marine electric drive of a range of small and medium capacities.Engines of this type are structurally simple and reliable, have rigid natural mechanical characteristics, do not require energy for excitation, have a large overload capacity and high speed in transients. Their distinctive feature is the high specific moment.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Preface

This issue of the Journal of Physics: Conference Series (JPCS) contains the proceedings of the 2023 3rd International Conference on Electronics, Circuits and Information Engineering (ECIE 2023). The conference took place in Suzhou, China during January 6th-8th, 2023 (virtual form), with the attendance of about 60 scholars, experts, researchers and scientists in related areas.ECIE 2023 is committed to creating an international cooperation and exchange platform for scientists, engineers, and practitioners in the fields related to electronics, circuits and information engineering to share their latest research and development results, discuss existing problems and challenges, and explore cutting-edge technologies. Everyone interested in these fields were welcomed to join the conference and to give comments and raise questions to the speeches and presentations.The conference agenda covered three parts, including a keynote speech delivered by four sophisticated professors from different countries and regions. Among them, Prof. Valentina E. Balas from Aurel Vlaicu University of Arad, Romania performed a dramatic keynote speech on Challenges in Green Computing Technologies and New AI regulations. The research proposed an interesting and hot topic related to Green Computing. She introduced their new research in de field of nanotechnologies brain-inspired proposed for the next generation of computing technologies and focused on developing very reliable nano-architecture with low power consumption. Also, she discussed sustainability and green computing and introduced the new AI regulations in EU. It was a wonderful opportunity for all the participants to interact with the experts and specialists to get their advice or suggestions. And we are very optimistic that all participants had acquired new ideas and knowledge from this conference to enhance the capability toward electronics, circuits and information engineering.Through a rigorous peer-review process, all the submitted papers were performed double blind review to check their quality of content, level of innovation, significance, originality and legibility. Based on the expertise review comments, some excellent papers were accepted and the corresponding authors were invited to submit their papers for final publication. The accepted papers included topics on: VLSI Design and Fabrication, Semiconductor Devices and Circuits, Parallel and Distributed Computing, test and Reliability, Electromagnetic Compatibility, etc.We would like to extend our sincere acknowledgement to all the keynote speakers, peer reviewers, and all the participants. Our special thanks also go to the Conference Chair and the International Technical Program Committee members for the procedures that lead to the organization of this event, to the members of IOP-JPCS for their patience while waiting for the final versions of the papers, to our colleagues who contributed to its realization.The Committee of ECIE 2023List of Committee member is available in this pdf.

Low Leakage CMOS Design Technique with Stable State Retention

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Reversible logic can provide lower switching energy costs relative to all irreversible logic, including those developed by industry in semiconductor circuits, however, more research is needed to understand what is possible. Superconducting logic, an exemplary platform for both irreversible and reversible logic, uses flux quanta to represent bits, and the reversible implementation may switch state with low energy dissipation relative to the energy of a flux quantum. Here we simulate reversible shift register gates that are ballistic: their operation is powered by the input bits alone. A storage loop is added relative to previous gates as a key innovation, which bestows an asynchronous property to the gate such that input bits can arrive at different times as long as their order is clearly preserved. The shift register represents bit states by flux polarity, both in the stored bit as well as the ballistic input and output bits. Its operation consists of the elastic swapping of flux between the stored and the moving bit. This is related to a famous irreversible shift register, developed prior to the advent of superconducting flux quanta logic (which used irreversible gates). In the base design of our ballistic shift register (BSR) there is one 1-input and 1-output port, but we find that we can make other asynchronous ballistic gates by extension. The gate constitutes the first asynchronous reversible 2-input gate. Finally, for a better insight into the dynamics, we introduce a collective coordinate model. We find that the gate can be described as motion in two coordinates subject to a potential determined by the input bit and initial stored flux quantum. Aside from the favorable asynchronous feature, the gate is considered practical in the context of energy efficiency, parameter margins, logical depth, and speed.

Improved epitaxy of CsI(Tl) film on Si substrate buffered by graphene for X-ray detection

The growth of the CsI(Tl) scintillators deposited on glass substrates with proper wavelength matching the mainstream semiconductor circuits is crucial for X-ray imaging industry. But the coupling loss between the scintillators and silicon based photo sensors has limited the performance. So fabricating CsI(Tl) films on monocrystalline silicon is greatly important for next-generation high performance X-ray image devices. However, the lattice and thermal mismatch between CsI(Tl) and Si always deteriorates the morphology and structure, and thus degrades the property of the CsI(Tl) scintillation converters. Here, by utilizing crystalline graphene(Gr) as a buffer layer, the van der Waals epitaxial growth of CsI(Tl) film on Si(111) substrate is reported and its advanced applications are demonstrated. The introduced graphene buffer layer extremely frees the stress between CsI(Tl) and Si substrate. Therefore, the CsI(Tl) films show perfect micro-columnar and crystalline structures, and then, exhibit much higher light output and signal to noise ratio, and better modulation transfer functions and a bar pattern X-ray image compared to that on bare Si(111) substrate. This facile method not only lays the foundation for the epitaxy of the alkali halide crystals, including CsI(Tl), onto Si-based detectors and its applications in radiation detection, but also may broaden a new perspective of deposition of CsI(Tl) scintillators into flexible substrates.

Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications

This paper summarizes the modulation configurations of phase locked loops (PLLs) and their integration in semiconductor circuits, e.g., the input modulation for cellular phones, direct-modulation for low power wireless sensor networks, feedback-loop modulation for high-speed transmission, and two-point modulation for short-range radio transceivers. In this survey, basic configuration examples of integrated circuits for wired and wireless applications which are using the PLL modulation configurations are explained. It is important to select the method for simply and effectively determining the characteristics corresponding to the specific application. The paper also surveys technologies for future PLL design for digitizing of an entire PLL to reduce the phase noise due to a modulation by using a feedback loop with a precise digital phase comparison and a numerically controlled oscillator with high linearity.

High-Performance C60 Coupled Ferroelectric Enhanced MoS2 Nonvolatile Memory.

Nonvolatile memory (NVM) devices based on two-dimensional (2D) materials have recently attracted widespread attention due to their high-density integration potential and the ability to be applied in computing-in-memory systems in the post-Moore era. Considering the high current on/off ratio, programmable threshold voltage, nonvolatile multilevel memory state, and extended logic functions, plenty of breakthroughs related to ferroelectric field-effect transistors (FeFETs), one of the most important NVM devices, have been made in the past decade. Among them, FETs coupled with organic ferroelectric films such as P(VDF-TrFE) displayed properties of remarkable robustness, easy preparation, and low cost. However, the dipoles of the P(VDF-TrFE) film cannot be flipped smoothly at low voltage, impeding the further application of organic FeFET. In this paper, we proposed a high-performance FeFET based on monolayer MoS2 coupled with C60 doped ferroelectric copolymer P(VDF-TrFE). The inserted C60 molecules enhanced the alignment of the dipoles effectively at low voltage, allowing the modified device to demonstrate a large memory window (∼16 V), high current on/off ratio (>106), long retention time (>10 000 s), and remarkable endurance under the reduced operating voltage. In addition, the in situ logic application can be realized by constructing facile device interconnection without building complex complementary semiconductor circuits. Our results are expected to pave the way for future low-consumption computing-in-memory applications based on high-quality 2D FeFETs.

Analysis of a p-i-n Diode Circuit at Radio Frequency Using an Electromagnetic-Physics-Based Simulation Method

Embracing the era of higher operating frequencies, expanding functionality, and increased integration scale, modern circuit design relies more and more on the accurate prediction of the electromagnetic (EM) effects resulting from undesired radiation and mutual coupling of digital electronic devices. In this paper, an electromagnetic-physics-based simulation method is proposed, to simulate semiconductor devices and circuits. It utilizes physics-based simulation to analyze semiconductor devices in a circuit and incorporates this physics-based simulation into electromagnetic simulation (e.g., the finite difference time domain (FDTD)), to simulate a circuit at high frequency. To validate the proposed method, sample numerical results on circuits containing a commercial p-i-n diode with model number mot_bal99lt1 at radio frequency (RF) were obtained and compared with measurement data. The comparison showed a good agreement between the two sets of data, which validated the feasibility and accuracy of the proposed algorithm. Moreover, the proposed method can provide a useful physical mechanism for understanding effects on semiconductor devices and circuits.

Design and Simulation of an Autonomous Molecular Mechanism Using Spatially Localized DNA Computation.

As a well-established technique, DNA synthesis offers interesting possibilities for designing multifunctional nanodevices. The micro-processing system of modern semiconductor circuits is dependent on strategies organized on silicon chips to achieve the speedy transmission of substances or information. Similarly, spatially localized structures allow for fixed DNA molecules in close proximity to each other during the synthesis of molecular circuits, thus providing a different strategy that of opening up a remarkable new area of inquiry for researchers. Herein, the Visual DSD (DNA strand displacement) modeling language was used to design and analyze the spatially organized DNA reaction network. The execution rules depend on the hybridization reaction caused by directional complementary nucleotide sequences. A series of DNA strand displacement calculations were organized on the locally coded travel track, and autonomous movement and addressing operations are gradually realized. The DNA nanodevice operates in this manner follows the embedded "molecular program", which improves the reusability and scalability of the same sequence domain in different contexts. Through the communication between various building blocks, the DNA device-carrying the target molecule moves in a controlled manner along the programmed track. In this way, a variety of molecular functional group transport and specific partition storage can be realized. The simulation results of the visual DSD tool provide qualitative and quantitative proof for the operation of the system.

Super-resolution method for SEM images based on pixelwise weighted loss function.

Scanning electron microscopy (SEM) has realized high-throughput defect monitoring of semiconductor devices. As miniaturization and complexification of semiconductor circuit patterns increase in recent years, so has the number of defects. There is thus a great need to further increase the throughput of SEM defect monitoring. Toward this end, we propose a deep learning-based super-resolution method that reproduces high-resolution (HR) images from corresponding low-resolution images. Image quality factors such as pattern contrast and sharpness are important in SEM HR images in order to evaluate the quality of printed circuit patterns. Our proposed method meets various image quality requirements by changing the loss calculation method pixelwise based on the pattern in the image. It realizes super-resolved images that compare favorably with actual HR images and can improve SEM throughput by 100% or more.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

Efficient protection and control of electric drives using solid state circuits

The paper presents the results of a theoretical study of semiconductor circuits carried out for practical use in the development of a non-contact switching and control apparatus for starting control and under voltage protection of AC motors. According to the results of the analysis of semiconductor circuits, it is recommended to use them when creating relay devices for the automation of electrical equipment. Theoretical investigated semiconductor circuits were used in the creation of a non-contact starter of an asynchronous electric drive with protection against operation at minimal voltage drops in the network.

An Optimal DPM Based Energy-Aware Task Scheduling for Performance Enhancement in Embedded MPSoC

Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip (MPSoC) has become an integral chip design issue for multiprocessor systems. The performance measurement of computational systems is changing with the advancement in technology. Due to shrinking and smaller chip size power densities on-chip are increasing rapidly that increasing chip temperature in multi-core embedded technologies. The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor (CMOS) circuits because high on-chip temperature adversely affects the life span of the chip. In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first (EA-EDF) scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip (SOC). Dynamic power management (DPM) enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration. Task migration avoids peak temperature values in the multi-core system. High utilization factor ( on central processing unit (CPU) core consumes more energy and increases the temperature on-chip. Our technique switches the core by migrating such task to a core that has less temperature and is in a low power state. The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core. The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works. The simulation results show the improvement in performance by optimizing 4.8% on 9%, 16%, 23% and 25% at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.