Low Leakage CMOS Design Technique with Stable State Retention

Abstract

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.