Selective Epitaxial Process Research Articles

Single-Mode Laser in the Telecom Range by Deterministic Amplification of the Topological Interface Mode.

Photonic integrated circuits are paving the way for novel on-chip functionalities with diverse applications in communication, computing, and beyond. The integration of on-chip light sources, especially single-mode lasers, is crucial for advancing those photonic chips to their full potential. Recently, novel concepts involving topological designs introduced a variety of options for tuning device properties, such as the desired single-mode emission. Here, we introduce a novel cavity design that allows amplification of the topological interface mode by deterministic placement of gain material within a topological lattice. The proposed design is experimentally implemented by a selective epitaxy process to achieve closely spaced Si and InGaAs nanorods embedded within the same layer. This results in the first demonstration of a single-mode laser in the telecom band using the concept of amplified topological modes without introducing artificial losses.

Monolithic integration of multicolor InGaN LEDs with uniform luminescence emission.

We report the demonstration of monolithic integration of multicolor LEDs with highly spatially uniform emission wavelength. LEDs with colors ranging from green to orange are realized in a single selective area epitaxy process, and pronounced emission peak with very narrow spectral linewidth from photonic crystal effect is also achieved simultaneously. The In contents and emission colors are tuned by precisely controlling the nanowire emitter diameter and spacing. The emission wavelengths exhibit small variations of only a few nanometers among countless individual nanowire emitters over a sub-mm2 area region.

Multi-kV Class β-Ga₂O₃ MESFETs With a Lateral Figure of Merit Up to 355 MW/cm²

We demonstrate over 3 kV gate-pad-connected field plated (GPFP) $\beta$-Ga$_2$O$_3$ lateral MESFETs with high lateral figure of merit (LFOM) using metalorganic vapor phase epitaxy (MOVPE) grown channel layers and regrown ohmic contact layers. Using an improved low-temperature MOVPE selective area epitaxy process, we show that a total contact resistance to the channel as low as 1.4 $\Omega$.mm can be achieved.The GPFP design adopted here using PECVD (plasma-enhanced chemical vapor deposition) deposited SiN$_x$ dielectric and SiN$_x$/SiO$_2$ wrap-around passivation exhibits up to ~14% improved R$_{ON}$, up to ~70% improved breakdown voltage (V$_{BR}$ = V$_{DS}$ - V$_{GS}$) resulting in up to $\sim$3$\times$ higher LFOM compared to non-FP $\beta$-Ga$_2$O$_3$ lateral MESFETs. The V$_{BR}$ (~2.5 kV) and LFOM (355 MW/cm$^2$) measured simultaneously in our GPFP $\beta$-Ga$_2$O$_3$ lateral MESFET (with L$_{GD}$ = 10 $\mu$m) is the highest value achieved in any depletion-mode $\beta$-Ga$_2$O$_3$ lateral device.

Hybrid III-V Silicon Photonic Crystal Cavity Emitting at Telecom Wavelengths.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.

Application of Cl2 for low temperature etch and epitaxy

In this work, two most typical applications of Cl2 etch relevant for sub-10 nm CMOS device production, namely sacrificial etch and selective deposition are presented. It is shown that Si0.7Ge0.3 sacrificial etch with Cl2 is possible in the temperature range of 350 °C–400 °C when He is used as a carrier gas. This temperature range can be further lowered when He is substituted with N2. Use of N2 also allows Si etch at very low temperatures (∼400 °C) which are not accessible for etching with HCl and potentially can be used for sacrificial etch of Si and Si-based epitaxial selective growth processes. Furthermore, a combination of Cl2 with high order Si and Ge precursors allowed development of cyclic selective epitaxial processes at temperatures as low as 400 °C with active dopant concentrations of ∼1 × 1020 cm−3 for Si0.7Ge0.3:B and ∼3 × 1019 cm−3 for Si0.7Ge0.3:P.

Investigation of Cl2 etch in view of extremely low temperature selective epitaxial processes

A Cl2 etch of different group IV materials in a low temperature range (260–600 °C) is presented. It is shown that in general the Cl2 etching behavior is very similar to that of HCl: Si is etched slowest, Ge fastest with SiGe being between these two cases. Activation energies for Cl2 etching of Si, SiGe and Ge are very low and show that neither Cl nor H surface passivation are limiting factors for the etch. The etching rate is strongly affected by the choice of the carrier gas (He, H2 and N2) and by the process pressure which gives high flexibility for its application. As compared to HCl, Cl2 allows decreasing of the etching process temperatures down to ∼400 °C for Si and ∼250 °C for Ge. Although it is not clear if co-flow selective processes are visible due to possible exothermic chain reaction of radicals in the presence of group IV hydrides, cyclic approaches can be relatively easily achieved at temperatures below 500 °C.

Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology

In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1−xGex (0.35≤×≤0.40) with boron concentration of 1×1020cm−3 was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825°C in order to in-situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780–800°C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an ALD approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics.

SiGe SEG Growth for Buried Channels p-MOS Devices

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.

Selective Epitaxial Growth of Si(Ge) for High Performance MOSFET Applications

Selective epitaxial growth of Si and SiGe films has been applied to the fabrication of many high-performance MOSFETs, because new device structures can be realized by selective epitaxial growth. Selective growth of Si(Ge) at the source/drain region is the most well-known example. Precise control of the selective epitaxial process enables the best performance with the desired structure. Control of the selectivity is also important for a robust manufacturing process. Selective epitaxial growth is essential for next-generation MOSFETs, such as FinFETs. Innovation of selective epitaxial growth will spur the continuous progress of MOSFETs.

Low-Voltage and High-Responsivity Germanium Bipolar Phototransistor for Optical Detections in the Near-Infrared Regime

Germanium (Ge) bipolar phototransistors with high-responsivity performance are demonstrated using a low-temperature selective Ge epitaxy process. Large photocurrent and optical response enhancement are achieved over a conventional p-i-n Ge photodetector, which is predominantly attributed to the current gain induced by transistor actions. When illuminated with a photon wavelength of 1.55 mum , a Ge phototransistor shows a large responsivity of ~ 2.0 A/W for a low operating bias <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VA</i> of 1.0 V. Optical measurement results further show that good photoresponse could be achieved for a spectral range of 1.31-1.62 mum, making such a device a very promising option for optical detections in the near-infrared (including <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> -band) wavelength regime.

Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.

A multiple quantum well integrated with a selectively grown quaternary layer

The multiple quantum well is an important backbone to a number of advanced III–V optoelectronic devices. These include semiconductor lasers, detectors and modulators. Increased device functionality can be achieved by monolithically integrating a multiple quantum well with a selectively grown bulk quaternary. We report on a method for fabricating a selectively deposited quaternary film integrated with a multiple quantum well in an MOCVD reactor. Selective area epitaxy is known to cause a composition shift in the deposited quaternary. Quantitative modelling of the selective area epitaxy process is used to determine the nominal group-III composition required to deposit a quaternary film such that the peak strain induced by the composition shift is minimized. Measurements using spatially resolved photoluminescence and surface profiling are reported to demonstrate the validity and usefulness of the model.

Raised source/drains for 50 nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

A selective epitaxy process for raised sources and drains is investigated, with growth performed at a pressure in the 1 Torr regime, rather than the more common CVD (10’s of Torr) or UHV–CVD (1–40 mTorr) regimes. It is shown that selective growth can be achieved using a mixture of silane and dichlorosilane without any requirement for Cl 2 or HCl in the gas stream. The selectivity of the process can be controlled by varying the silane:dichlorosilane ratio in the gas mixture, with a ratio between 1:1 and 3:1 giving selective growth. Facet-free selective epitaxy is achieved, the process is selective to silicon nitride and a growth activation energy of 2.4 eV is obtained. Raised source/drain MOSFET devices with channel lengths down to 50 nm have been fabricated and the thickness of the selective epitaxial silicon layer has been varied to investigate the effect of this parameter on device performance. Excellent sub-threshold characteristics are obtained and the sub-threshold slope, S, improves from 102 to 81.9 mV/dec as the raised source/drain thickness is increased from 50 nm to 100 nm. The raised source/drain also improves threshold voltage roll-off and drain induced barrier lowering. A decrease in both I on and I off is seen with increasing RSD thickness, but the overall I off/ I on trade-off is unchanged.

Selective epitaxial growth using dichlorosilane and silane by low pressure chemical vapor deposition

In this paper, an HCl-free silicon selective epitaxy process is presented. The low pressure chemical vapor deposition (LPCVD) process uses a mixture of silane and dichlorosilane in hydrogen. The selective growth conditions are established by varying the growth temperature and the proportion of dichlorosilane in the gas mixture. Highly selective silicon epitaxial layers with smooth morphology are obtained within a wide range of growth temperatures. No apparent local loading effect is observed. The use of both DCS and silane provides a means to adjust the silicon growth rate by allowing independent control of the etching component (dichlorosilane) and the growth component (silane). The independent control of etching and growth components of the overall chemistry makes it possible to increase the silicon on oxide incubation period, allowing the fabrication of devices where long epitaxial growth times are needed.

Selective epitaxial growth using dichlorosilane and silane by low pressure chemical vapor deposition

In this paper, an HCl-free silicon selective epitaxy process is presented. The low pressure chemical vapor deposition (LPCVD) process uses a mixture of silane and dichlorosilane in hydrogen. The selective growth conditions are established by varying the growth temperature and the proportion of dichlorosilane in the gas mixture. Highly selective silicon epitaxial layers with smooth morphology are obtained within a wide range of growth temperatures. No apparent local loading effect is observed. The use of both DCS and silane provides a means to adjust the silicon growth rate by allowing independent control of the etching component (dichlorosilane) and the growth component (silane). The independent control of etching and growth components of the overall chemistry makes it possible to increase the silicon on oxide incubation period, allowing the fabrication of devices where long epitaxial growth times are needed.

(Selective) Epitaxial Growth of Strained Si to Fabricate Low Cost and High Performance CMOS Devices

ABSTRACTTensile strained Si on SiGe Strain Relaxed Buffers (SRB) is an interesting candidate to increase both electron and hole mobility which results in improved device performance. Most of this work was/is based on thick (several μm), step-graded SRBs with or without Chemical Mechanical Polishing (CMP) planarisation. This approach bears several disadvantages such as issues with STI formation in the thick SiGe structure, and considerable self-heating effects due to the lower thermal conductivity of the SiGe material. Further, pMOS improvement requires SRBs with high Ge contents (&gt; 30 %), which complicates device fabrication even more. To overcome these issues, we developed a new and cost efficient type of thin SRB (∼200 nm). The concept is based on the introduction of a thin carbon-containing layer during growth of a constant composition SiGe layer. The process relies on standard Chemical Vapor Deposition epitaxial technology without need for CMP. It is designed to allow both non-selective growth on blanket wafers and selective growth in the active area of structured wafers with Shallow Trench Isolation (STI). The selective epitaxial process for strained Si on thin SRBs proposed here, allows relatively simple and cost-effective fabrication of strained Si layers on existing STI structures without any process modification. Further, it offers a very flexible fabrication scheme to independently improve nMOS and pMOS devices. The SRB quality is comparable to the best reported in literature so far, with 70 % and 53 % mobility enhancements for long channel nMOSFETs on 22 % Ge SRBs grown on blanket and STI patterned wafers, respectively.

Characterization of leakage current related to a selectively grown collector in SiGeC heterojunction bipolar transistor structure

Sources of base-collector and base-emitter leakage current in a SiGeC-based heterojunction bipolar transistor (HBT) with a selectively grown and chemical–mechanical polished (CMP) collector are discussed. Transmission electron microscopy and electrical measurement have been applied to investigate the leakage current. It has been demonstrated that the edge-located defects generated by selective epitaxy process are the origin of the junction leakage.

Selective SiGe epitaxy by rtcvd for new device architectures

CMOS technologies and devices are approaching their theoretical limits such as optical lithography, gate oxide thickness, etc. Consequently, new efforts are made in order to improve or modify device architecture. New epitaxial films grown at low temperature have potential of improving both electrical performances and integration of advanced devices. Firstly, we investigate the selective SiGe epitaxy with high Ge content based on the DCS/GeH 4/HCl/H 2 chemistry using an industrial 200 mm single wafer chemical vapour deposition at reduced pressure (<40 Torr) and low temperature (600–750 °C). We present new results about global loading effects in terms of growth and Ge content (15–40%) of perfectly strained SiGe films used for their selective etch properties in new device architectures. Secondly, we report on morphological results of the novel CMOS device architecture called silicon-on-nothing (SON). They allow extremely thin (a few nanometers) buried dielectric and silicon films to be fabricated with high resolution and uniformity guaranteed by SiGe and Si selective epitaxial processes. It is a very permissive structure as first approach of ultra thin SOI films.

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices. Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f T and f max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT. The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.

A self-aligned epitaxially grown channel MOSFET device architecture for strained Si/SiGe systems

We describe the fabrication of a self-aligned epitaxially grown channel MOSFET device suitable for the strained Si/SiGe systems. This device architecture relies on a selective epitaxy process to achieve self-alignment and contact formation of the source and drain. It is also amenable in a conventional Si VLSI manufacturing environment. Difficulties encountered with growing high quality source/drain contacts to the channel layer were highlighted and a novel solution was proposed. Structural as well as electrical characterisation of the completed devices are presented.