Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

Abstract

Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.