Selective Epitaxial Process Research Articles

Facet‐Free Selective Silicon Epitaxy by Reduced‐Pressure Chemical Vapor Deposition Process Evaluation and Impact on Shallow Trench Isolation

A facet‐free, selective epitaxy process has been identified using the chemistry in single‐wafer reduced‐pressure chemical vapor deposition. The process window has been explored with respect to shallow trench isolation, simultaneous polycrystalline silicon (polysilicon) deposition, facet formation, and electrical parameters of polysilicon sheet resistance and junction leakage current. The isolation structure can be severely degraded by aggressive pre‐epitaxy bakes through volatile SiO formation; however, the impact is minimized when the prebake is limited to 900°C, 60 s. Concurrent deposition of polysilicon and silicon epitaxy can result in significantly different deposition rates. Low process pressures result in greater relative epitaxy growth rates and high pressures result in lower relative epitaxy deposition rates. The facet‐free process depends heavily on both the gate sidewall structure and the process conditions, where the combination of an undercut into the pad oxide and the nitride sidewall with the process pressure yield a reliably facet‐free process. Electrical results demonstrate that standard Ti or Co self‐aligned silicidation can be extended into a 0.1 μm gate length regime. © 1999 The Electrochemical Society. All rights reserved.

Development of Metal-Organic Vapor Phase Diffusion Enhanced Selective Area Epitaxy, a Novel Metal-Organic Vapor Phase Epitaxy Selective Area Growth Technique, and Its Application to Multi-Mode Interference Device Fabrication

For the first time Multi-Mode Interference (MMI) power splitters have been fabricated directly by selective area growth, using a novel metal-organic vapor phase diffusion enhanced selective area epitaxy (MOVE2) process. The MOVE2 process features extremely wide-range in-plane bandgap control, high design flexibility and good uniformity under conventional growth pressure and therefore is very suitable for photonic integration. For bulk InGaAs material in-plane bandgap shifts as large as 200 nm have been obtained. The general incorporation characteristics of both group-III and group-V species in selective area grown InGaAsP have also been determined. The MMI power splitter excess losses were as low as 2 dB, including S-bend losses.

Facet Free Selective Silicon Epitaxy by Rapid Thermal Chemical Vapor Deposition

ABSTRACTA facet-free, selective epitaxy process has been identified using the SiH2CI2 /HCI/H2 chemistry in a commercially available, single-wafer epitaxy reactor. The pre-epitaxy bake required a minimum of 900°C in order to obtain a clean silicon surface with reasonable throughput while preserving the integrity of the shallow trench isolation structures. The epitaxy growth rate ranged from as low as 130Å/rnin at 825°C, 10 torr to as high as 1500 Å/min at 875°C and 70 torr while the deposition rate of polysilicon on polysilicon differed significantly: at 10 torr, the epitaxy growth rate is greater by as much as 50%, and at 70 torr the polysilicon deposition rate is greater by as much as 40%. The facet suppression depended heavily on two things: the undercut beneath the polysilicon gate sidewall insulator and the process pressure. The undercut is believed to be responsible for suppressing the initial stage of facet formation, most probably by completely eliminating lateral overgrowth of the crystal. The process conditions then enable continued facet suppression perhaps by restricting the silicon surface mobility. The sidewall structure and process conditions combine to make a reliably facet-free selective epitaxy process

Polycrystalline Si Films Fabricated by Low Temperature Selective Nucleation and Solid Phase Epitaxy Process

AbstractWith a selective nucleation and solid phase epitaxy (SNSPE) process, grain sizes of 10 μm have been achieved to date at 620°C in 100 nrm thick silicon films on amorphous SiO2, with potential for greater grain sizes. Selective nucleation occurs via a thin film reaction between a patterned array of 20 rnm thick indium islands which act as heterogeneous nucleation sites on the amorphous silicon starting material. Crystal growth proceeds by lateral solid phase epitaxy from the nucleation sites, during the incubation time for random nucleation. The largest achievable grain size by SNSPE is thus approximately the product of the incubation time and the solid phase epitaxy rate. Electronic dopants, such as B, P, and Al, are found to enhance the solid phase epitaxy rate and affect the nucleation rate.

Thin dielectric degradation during silicon selective epitaxial growth process

A fundamental issue in silicon selective epitaxial growth (SEG) processes is the impact of the pre-epitaxy silicon surface treatments and the SEG ambient on the properties of thin insulating materials exposed to the preclean environment. In this study, we compare pinhole formation in 10–50 nm thermal oxides with more robust oxide/nitride composites of similar thickness. The degradation of thin thermal oxide is attributed to pinhole formation and expansion in the ultrathin oxide layers during ex situ pre-epi surface treatments, in situ H2 prebake, and selective epitaxial deposition process. The superior resistance of oxide/nitride/oxide (ONO) structures to dielectric degradation may be attributed to the existence of the sandwiched silicon nitride layer which suppresses the mechanism of oxide decomposition during the pre-epitaxy wet cleaning, and the selective epitaxial growth processes.

Steric and electronic interactions between source gas and substrate surface during the Al-CVD/Al selective epitaxy process as investigated by quantum chemical calculations

We have performed quantum chemical calculations by semiempirical MNDO and by density functional theory (DFT) to rationalize the selection of an Al source gas for the selective Al-CVD/Al process. The electronic properties of Al(CH 3) n H 3− n , ( n = 0 to 3) and their adsorption complexes over representative aluminum metal clusters were calculated. Initially, the interaction of Al source gases with a representative Al metal was studied by both MNDO and DFT methods and the results were found to be qualitatively comparable. Further detailed calculations were performed by MNDO to understand the interaction of Al(CH 3) n H 3− n with larger cluster models of Al substrate as well as insulator silica surface. The results of the calculations indicate that the interaction energy between the substrate and the source are controlled by both steric and electronic factors. The steric factor favors the interaction of unsubstituted hydride, namely aluminum trihydride and the electronic factor favors the interaction of maximum substituted aluminum organic, namely trimethyl aluminum with the substrates. However, dimethyl aluminum hydride has the most favorable interaction energy with the Al metal, since it has the right combination of steric and electronic factors. The interaction energy of DMAH with chlorided silica surface is more favorable than the untreated silica surface.

Selective epitaxy of compound semiconductors: novel sources

The development of selective epitaxial techniques has centred on the use of conventional precursors such as trimethyl gallium in combination with AsH3. Recently, the development of new precursors, such as diethyl gallium chloride, or the use of conventional precursors in conjunction with HCl or AsCl3 has offered greater flexibility in the development of a selective-area epitaxial process. In addition, wide process windows have been demonstrated whereby excellent material properties and high selectivity can be achieved under typical MOVPE conditions. This compatibility with conventional MOVPE growth conditions allows for the integration of selective-area growth into the existing MOVPE growth processes. This paper will present recent results on the development of these alternative precursors for selective-area growth. The achievement of a selective epitaxial process is discussed in terms of the chemistry of the inorganic-based growth techniques.

Thin dielectric behavior and boron penetration under high temperature H2 SEG prebake

During selective epitaxial Si growth the wafers are exposed to a H 2 rich atmosphere. The impact of high temperature hydrogen prebake, typical of selective Si epitaxial processes, on thin dielectrics is investigated. A prebake temperature range of 850°C to 1000°C was studied. MOS capacitors with n+ and p+ gates and 8.5nm oxides and plasma nitrided oxides are examined. For p+ MOS with non-nitrided gate oxides massive boron penetration occurs. In contrast, nitrided oxides are found to be highly immune to hydrogen induced boron penetration and exhibit a low interface state density for either n+ or p+ gate samples.

Power GaAs MESFET with a High Drain-Source Breakdown Voltage

A power GaAs MESFET with a high drain-source breakdown voltage in excess of 17 V has been developed. A selective GaAs epitaxial process is introduced to form "inlaid" n+ source and drain regions that can provide a high drain-source breakdown voltage and a low ohmic-contact resistance. Typical characteristics of the MESFET composed of two-cell units are as follows: