Facet‐Free Selective Silicon Epitaxy by Reduced‐Pressure Chemical Vapor Deposition Process Evaluation and Impact on Shallow Trench Isolation

Abstract

A facet‐free, selective epitaxy process has been identified using the chemistry in single‐wafer reduced‐pressure chemical vapor deposition. The process window has been explored with respect to shallow trench isolation, simultaneous polycrystalline silicon (polysilicon) deposition, facet formation, and electrical parameters of polysilicon sheet resistance and junction leakage current. The isolation structure can be severely degraded by aggressive pre‐epitaxy bakes through volatile SiO formation; however, the impact is minimized when the prebake is limited to 900°C, 60 s. Concurrent deposition of polysilicon and silicon epitaxy can result in significantly different deposition rates. Low process pressures result in greater relative epitaxy growth rates and high pressures result in lower relative epitaxy deposition rates. The facet‐free process depends heavily on both the gate sidewall structure and the process conditions, where the combination of an undercut into the pad oxide and the nitride sidewall with the process pressure yield a reliably facet‐free process. Electrical results demonstrate that standard Ti or Co self‐aligned silicidation can be extended into a 0.1 μm gate length regime. © 1999 The Electrochemical Society. All rights reserved.