Selective CVD Research Articles

Reduction of dislocation density in single crystal diamond by Ni-assisted selective etching and CVD regrowth

The development of large-area diamond films with low dislocation density plays a key role in diamond-based devices. In this study, we present a straightforward and reasonably priced Ni-assisted etching and re-growth method to decrease the dislocation density of diamond. By adjusting the annealing temperature, a high-density inverted pyramid and/or trapezoidal pit can be effectively exposed because the interaction between carbon and Ni metal. The Ni tends to dissolve the diamond surrounding the dislocation at high temperature while maintaining the surface's flatness. The precipitated graphite layer is removed using wet etching, and the step flow mode is then restored via the re-growth procedure. It shows that the dislocations located beneath the etching pits are partially annihilated during the lateral coalescence, resulting in a decrease in dislocation density.

Study of Cu-growth feature by selective low-pressure chemical vapor deposition using a CuI precursor

In this study, Cu-growth features are investigated using selective low-pressure CVD of Cu on Ru(001) using a copper(I) iodide precursor. While discrete columnar grains are formed below 320 °C, lateral Cu islands are grown above 380 °C. The CuI dissociation efficiency, which depends on the growth temperature, indicates two activation energies corresponding to I2 desorption from Cu and Ru. The activation energy below 320 °C and above 380 °C are identified as the energies required for the desorption of I2 from Cu(111) and Ru(001), respectively. At 400 °C, nucleation occurs at the initial stage, followed by the lateral growth of Cu-islands. A proposed growth model, involving dissociated Cu-atom contributions toward increasing the Cu-island height and Cu coverage on Ru, can explain the island growth features dependent on the growth time. Further, the growth model reveals an important factor to achieve thinner Cu layers growth entirely covering Ru.

Area selective CVD of metallic films from molybdenum, iron, and ruthenium carbonyl precursors: Use of ammonia to inhibit nucleation on oxide surfaces

The authors demonstrate that the addition of an ammonia coflow during the chemical vapor deposition of MoCxNy, Fe, or Ru thin films at ≤200 °C from the metal carbonyl precursors Mo(CO)6, Fe(CO)5, or Ru3(CO)12 affords area-selective growth: film grows readily on titanium metal or vanadium nitride substrate surfaces, but no nucleation occurs on air-exposed SiO2, TiO2, Al2O3, or MgO within the investigated times of 1–2 h. By contrast, in the absence of ammonia, nucleation and deposition on these oxide surfaces can either be slow or rapid, depending strongly on the oxide surface preparation. NH3 is also the source of N in MoCxNy, which has a resistivity of 200 μΩ cm and becomes superconducting at a critical temperature of 4 K. The authors hypothesize that the passivating effect of NH3 on oxide surfaces involves site blocking to prevent precursor adsorption, or an acid–base interaction to stabilize surface-bound metal subcarbonyl intermediates, or a combination of these mechanisms. A key finding is that surface selective growth is often crucially dependent on the sample history of the substrate, which must be specified in detail if reproducible results are to be obtained.

Selective growth of two-dimensional phosphorene on catalyst surface.

Although the study of black phosphorene (BP) and its isomers has attracted enormous attention, the method of synthesizing high-quality samples in a large area is still pending. Here we explore the potential of using the chemical vapor deposition method to synthesize large-area two-dimensional (2D) phosphorene films on metal surfaces. Our ab initio calculations show that BP can be synthesized by using tin (Sn) as a catalyst, while one of its isomers, blue phosphorene (BLP), is very possible to be synthesized by using most other metals, such as Ag and Au. Besides, our study also suggests that the large binding energy between the 2D phosphorene and the active metal substrate may prohibit the exfoliation of the 2D phosphorene for real applications and, therefore, tin, silver and gold are predicted to be the most suitable catalysts for the synthesis of BP and BLP.

Controlled Selective CVD Growth of ZnO Nanowires Enabled by Mask‐Free Fabrication Approach using Aqueous Fe Catalytic Inks

AbstractFabrication process that enables selective growth of vertically oriented zinc oxide (ZnO) nanowires (NWs) via chemical vapor deposition method and mask‐free patterning approach is reported. It is shown that synthesis of high‐quality ZnO nanowires in various architectures is achievable by optimizing the growth conditions and by precise patterning of catalytic ink precursors. Parallel direct‐write patterning method is utilized to fabricate arrays of different architectures on Si/SiO2 substrates and directly on devices at preselected locations. The production of high‐quality, crystalline ZnO NWs is demonstrated using aqueous iron catalytic inks. The composition of the ink and the lateral size of the patterns deposited on substrates are shown to affect the resulting nanowires and thus, allowing to control the geometry (length and diameter) of the individual ZnO NWs in the patterned assemblies. The results indicate that our protocols are tailored to the fabrication of ZnO NWs with specific surface geometries and interface functionalities for variety of targeted device applications.

DURAL ARTERIOVENOUS MALFORMATIONS – CASE REPORT AND REVIEW OF THE LITERATURE

The gold standard in dural arteriovenous fistulas (DAVF) evaluation is complete angiography. Treatment options include: conservative management, open surgery, endovascular therapy, stereotactic radiosurgery or multimodality therapy. The goal of microsurgical intervention is DAVF obliteration or selective CVD disconnection. We present a 59 years old male who was brought to the Emergency Department of the National Institute of Neurology and Neurovascular Diseases in a comatose state (GCS- 5p).

Free-standing nanomembranes based on selective CVD deposition of functional poly-p-xylylenes.

The precise engineering of ultrathin nanofilms with variable functionality remains an unmet challenge in nanotechnology. We report a strategy for generating free-standing nanomembranes based on the selective chemical vapor deposition polymerization of functional [2.2]paracyclophanes on micropatterned self-assembled monolayers of alkanethiolates on gold. This fabrication strategy can yield microstructured nanofilms that are between 2 and 5 nm thick. Subsequent release from the substrate results in free-standing nanoscale membranes with controlled pore size and geometry. The process allows for modification of important functional parameters, such as ultrasmall membrane thickness, membrane pore geometry, and chemical functionality.

High Ge fraction intrinsic SiGe-heterochannel MOSFETs with embedded SiGe source/drain electrode formed by in-situ doped selective CVD epitaxial growth

High performance high Ge fraction intrinsic Si 1 − x Ge x -heterochannel MOSFETs with embedded Si 1 − x Ge x source/drain electrodes fabricated by the use of a low thermal budget process below 700 °C are demonstrated for the first time. The carrier mobility is very high in spite of high concentration impurity doping to the substrates for the threshold voltage control. It is suggested that this superior device characteristic is caused by suppression of impurity diffusion into the Si 1 − x Ge x -heterochannel, the high Ge fraction in the Si 1 − x Ge x -heterochannel and compressive stress applied to the Si 1 − x Ge x -heterochannel due to the embedded Si 1 − x Ge x source/drain.

Investigation into the selectivity of CVD iron from Fe(CO) 5 precursor on various metal and dielectric patterned substrates

It has been shown that CVD iron from a Fe(CO) 5 precursor deposits selectively on dielectric surfaces over tungsten surfaces. No similar selective CVD mechanism for titanium and aluminium to SiO 2 surfaces was observed. It was established that the selectivity between the tungsten surface and the SiO 2 surface could be enhanced through the oxidation of the tungsten surface. Depositions carried out on oxidised tungsten (WO X ) and SiO 2 substrates showed that iron layers up to 0.5 μm thick with a resistivity of 18 μΩcm can be deposited with excellent selectivity. The selective mechanism is attributed to the electrochemical properties of the tungsten or WO X layer, which prevents the reduction of the iron precursor. Selectivity loss was attributed to defects or impurities adsorbed to the tungsten surface.

Multiple Self-Aligned Iron Nanowires by a Dual Selective Chemical Vapor Deposition Process

have also been reported. In this paper, we demonstrate a self-aligning technique that allows the fabrication of organized parallel iron nanowires on a planar edge silicon and silicon dioxide surface. The desired number of parallel wires is formed by repeating a series of polysilicon deposition and oxidation steps. The planarized surface for nanowire formation was defined by CMP and the iron wires were produced using a novel double selective CVD process. In this work, tungsten hexafluoride WF6 and iron pentacarbonyl FeCO5 were the respective tungsten and iron precursors. The dimensions and spacing of the iron wires were determined by the thickness of the thermal oxide and deposited polysilicon layer respectively, and not by any lithographic tool. Very accurate alignment was achieved with this method. The multiple iron nanowires proposed in this paper have possible applications in magnetic field measurement and calibration devices in pressure sensing where the resistivity of long thin iron resistors changes under stress. Possibly the most interesting application for this technology is in the formation of tunable diffraction gratings. Under the influence of an electromagnetic field, the properties of the iron will change, which may allow a switching mode in the grating. Figure 1 shows substrate preparation and the deposition of multiple parallel iron nanowires. 4 m deep trenches were etched into the silicon substrates in an inductively coupled plasma ICP system with SF6 and C4F8 plasmas Fig. 1a. The trenches were then refilled

Uniform and selective CVD growth of carbon nanotubes and nanofibres on arbitrarilymicrostructured silicon surfaces

Carbon nanotubes (CNTs) and nanofibres (CNFs) are grown on bulk-micromachinedsilicon surfaces by thermal and plasma-enhanced chemical vapour deposition (PECVD),with catalyst deposition by electron beam evaporation or from a colloidal solution ofcobalt nanoparticles. Growth on the peaked topography of plasma-etched silicon‘micrograss’ supports, as well as on sidewalls of vertical structures fabricated bydeep-reactive ion etching demonstrates the performance of thermal CVD andPECVD in limiting cases of surface topography. In thermal CVD, uniform films oftangled single-walled CNTs (SWNTs) coat the structures despite oblique-angleeffects on the thickness of the catalyst layers deposited by e-beam evaporation.In PECVD, forests of aligned CNFs protrude from areas which are favourablywet by the colloidal catalyst, demonstrating selective growth based on surfacetexture. These surface preparation principles can be used to grow a wide variety ofnanostructures on microstructured surfaces having arbitrary topography, givingsubstrates with hierarchical microscale and nanoscale surface textures. Such substratescould be used to study cell and neuronal growth, influence liquid–solid wettingbehaviour, and as functional elements in microelectronic and micromechanical devices.

High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD

The improvement of current drivability and short channel effect is very important for ultrasmall MOS devices technology. SiGe-channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super self-aligned shallow junction electrode (S3E) MOSFETs formed by selective B-doped SiGe CVD are effective for the suppression of short channel effect. In this paper, it is clarified that the (S3E) pMOSFETs with Si0.65Ge0.35-channel are realized not only with suppression of punch through due to the ultrashallow B-diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si-channel fabricated by the same process conditions.

Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects

Self-aligned barriers on copper are widely investigated as a promising solution to replace standard PECVD dielectric barriers for the 65 nm technology node and beyond. As an alternative to electroless or selective CVD deposition, CuSiN barriers, based on the controlled modification of copper surface using a sequential exposure to SiH4 flow and NH3 plasma has been proposed. This paper focuses on the key role played by SiH4 flow on the physical and electrical barrier characteristics and more particularly on the existing relation between silane flow and Ta atoms from the TaN/Ta metal barrier. Non-regular defects observed after electromigration tests were not only attributed to intentionally modified copper surface but also to the presence of Ta atoms that diffused through copper lines during the tests.

Copper Penetration into Porous Ultra‐low‐κ Methyl Silsesquioxane during Selective CVD

Copper is deposited on nanoporous methyl silsesquioxane (MSQ) from Cu(thd)2. The process, which is carried out at 217 °C, well below the thermal decomposition temperature of Cu(thd)2, and in the presence of H2, results in the penetration and accumulation of copper at the interface between the dielectric layer and the substrate. This is demonstrated by both SEM and RBS, which show that significant selective growth takes place inside the dielectric and there is still no detectable deposition on the surface even after 100 nm growth is achieved.

Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drain layers

Fully-depleted 20-nm SOI complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) were successfully fabricated without a raised source/drain (S/D) structure, instead using low-temperature selective tungsten CVD (SWCVD) technology that can reduce the S/D series resistance. The thickness of the residual SOI layer under the W-clad layer in the S/D region was 6 nm for an nMOSFET and 9 nm for a pMOSFET. For 0.15-/spl mu/m-gate CMOSFETs, the subthreshold swings were 70 and 75 mV/dec for the nMOSFET and pMOSFET, respectively. The effectiveness of SWCVD technology when applied to ultrathin SOI devices was confirmed by small Si consumption and good continuity between the W and SOI layers. We expect that the S/D series resistance can be reduced to less than 1 k/spl Omega/-/spl mu/m by optimizing the S/D implantation conditions.

Crystallographic Structures and Parasitic Resistances of Self-Aligned Silicide TiSi2/Self-Aligned Nitrided Barrier Layer/Selective Chemical Vapor Deposited Aluminum in Fully Self-Aligned Metallization Metal Oxide Semiconductor Field-Effect Transistor

In deep submicron metal oxide semiconductor field-effect transistor (MOSFET) structures, parasitic resistances of source/drain and gate (S/D&G) regions limit device performance. For the reduction of parasitic resistances, we have previously proposed a fully self-aligned metallization (FSAM) MOSFET using selective aluminum chemical vapor deposition (Al CVD) technology. The features of FSAM-MOSFET are (1) self-aligned silicide (SALICIDE) for low TiSi2/n+-Si contact resistances in S/D regions, (2) self-aligned barrier layer on TiSi2 surface, and (3) selective Al deposition on S/D&G regions for low sheet resistances. In this study, crystallographic structures and parasitic resistances of SALICIDE TiSi2/self-aligned nitrided barrier layer/selective CVD Al structures have been investigated. It has been experimentally confirmed that (1) C49-TiSi2/n+-Si has lower contact resistance than C54-TiSi2/n+-Si, (2) the 10 nm amorphous Ti–Si–N barrier layer has stable thermal endurance and does not increase the contact resistances, and (3) the selective CVD Al layer reduces the sheet resistances of the S/D. Therefore, the combination of SALICIDE TiSi2, self-aligned barrier layer and selective CVD Al is promising for the low-temperature FSAM-MOSFET process.

Prevention of Corner Voiding in Selective CVD Deposition of Titanium Silicide on SOI Device

AbstractIn the application of selective CVD of titanium silicide to SOI devices, voids were observed at the bottom corner of the spacers, which caused reduction of drain current and in extreme cases formed an open circuit. Test structures were constructed to monitor void formation. It was found the voiding became serious when the thickness of the Si film was reduced. Adjusting the deposition condition by reducing the TiCi4 flow rate or by using a two-step deposition process was able to significantly reduce the chance of void formation. On very thin Si films, voiding can be prevented by depositing a selective Si layer prior to silicide deposition.

The Future Of Silicide For CMOS Contacts

AbstractThis paper examines the challenges for silicide contacts in current and future CMOS technologies and assesses the capability of TiSi2 and related materials, as well as CoSi2, to meet the technology requirements. Specific issues such as maintaining low resistance in narrow lines, source/drain silicon consumption, and silicide thermal budget, are discussed. In this regard we evaluate the salient features of the basic titanium salicide process, and variations such as alloying, implantation, selective CVD, and laser silicidation. Data are presented from recent experiments to assess progress in each approach towards meeting the necessary goals. Finally, projections of the future of silicide processing are given.

Selective Aluminum CVD on Si(100) From DMAH

AbstractThe influence of the dose on the crystal growth and on the selectivity of the Al-CVD process has been studied. Doses were varied from 100 L to 18000 L. Selective deposition was observed, both on passivated Si vs. SiO2, as well as on bare Si vs. passivated Si. On oxide elongated crystals have been deposited with dimensions of 1200 × 60 × 60 nm.

Is Selective Cvd an Improvement for the Titanium Silicide Process in Sub-Quarter Micron Technology? A Phase Formation Study Using X-Ray Diffraction

ABSTRACTThe C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 106 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl4 and SiH4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.