Abstract
In deep submicron metal oxide semiconductor field-effect transistor (MOSFET) structures, parasitic resistances of source/drain and gate (S/D&G) regions limit device performance. For the reduction of parasitic resistances, we have previously proposed a fully self-aligned metallization (FSAM) MOSFET using selective aluminum chemical vapor deposition (Al CVD) technology. The features of FSAM-MOSFET are (1) self-aligned silicide (SALICIDE) for low TiSi2/n+-Si contact resistances in S/D regions, (2) self-aligned barrier layer on TiSi2 surface, and (3) selective Al deposition on S/D&G regions for low sheet resistances. In this study, crystallographic structures and parasitic resistances of SALICIDE TiSi2/self-aligned nitrided barrier layer/selective CVD Al structures have been investigated. It has been experimentally confirmed that (1) C49-TiSi2/n+-Si has lower contact resistance than C54-TiSi2/n+-Si, (2) the 10 nm amorphous Ti–Si–N barrier layer has stable thermal endurance and does not increase the contact resistances, and (3) the selective CVD Al layer reduces the sheet resistances of the S/D. Therefore, the combination of SALICIDE TiSi2, self-aligned barrier layer and selective CVD Al is promising for the low-temperature FSAM-MOSFET process.
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