Selective CVD Research Articles

Self-aligned metal/IDP Si bipolar technology with 12-ps ECL and 45-GHz dynamic frequency divider

Ultra-high-speed operation using a self-aligned stacked metal/in situ doped poly-Si (IDP) (referred to as SMI) Si bipolar transistor technology that offers low base resistance while keeping collector capacitance low is demonstrated. This SMI technology provides a base electrode consisting of metal and in situ boron-doped poly-Si (IBDP). Here, metal is fully stacked on the IBDP by using selective tungsten CVD in the self-aligned manner, which means that the structure has low sheet resistance and the fabrication process has a small thermal budget. Thus, low base resistance and low collector capacitance can be achieved. Three types of base electrode, an IBDP, a partially stacked SMI, and a fully stacked SMI, were fabricated to investigate the usefulness of this SMI technology and the importance of the low base resistance. Using the SMI technology, the base resistance was reduced to about 40% and the maximum oscillation frequency was raised by about 30% with respect to the conventional poly-Si base electrode. This technology makes it possible to obtain ultra-high-speed operation with a 12-ps gate-delay emitter-coupled logic (ECL) circuit, and with 45-GHz-dynamic and 28-GHz-static frequency dividers, even when using a conventional ion-implanted base.

12-ps ECL using low-base-resistance Si bipolar transistor by self-aligned metal/IDP technology

A self-aligned metal/IDP (SMI) technology is proposed to reduce the external base resistance and to enable fabrication of high-speed bipolar transistors. This SMI technology produces a self-aligned base electrode of stacked layers of metal and in situ-doped poly-Si (LDP) with a small thermal budget by selective tungsten CVD. It provides the low base resistance and a shallow link base for the small-collector capacitance and the high-cutoff frequency. The base resistance is reduced to a half that in a transistor having a conventional poly-Si base electrode. A maximum oscillation frequency of 81 GHz and a 12.2-ps gate delay time in an ECL ring oscillator at a voltage swing of 250 mV were achieved by using the SMI technology even with an ion-implanted base.

Precursor design and selective aluminum CVD

Area-selective AI CVD technology has an excellent potential for filling via and contact holes of multilevel interconnection in Si ULSI. In this article, we discuss the selective AI CVD using metalorganic sources of trimethylaluminum [(CH 3) 3AI, TMA] and dimethylaluminum hydride [(CH 3) 2AIH, DMAH]. In order to deposit AI from TMA, the TMA molecule should be selectively excited into a reactive species of (CH 3) 2AI in the well controlled H 2/rf plasma. When using DMAH and H 2, AI can be deposited by low-pressure CVD; the features are (1) single crystal AI on Si surface, (2) filling capability into 0.3 μmΦ/1 μm-deep contact holes, (3) low contact resistivity (2 × 10 −7Ωcm 2) to n + − Si, and (4) erosion free at the Al/Si interface after 450 °C/30 min annealing. As a selective AI growth mechanism on the Si surface, we have proposed and experimentally confirmed a “surface electrochemical reaction model”. In this model, terminated-H on the Si surface reacts with CH 3-radical of the DMAH molecule to produce volatile CH 4. The H atom of the DMAH remains on the newly deposited AI surface as a newly terminated-H atom. The terminated-H atom on the surface reacts repeatedly with CH 3-radical to deposit AI. It is noted that, in the DMAH molecule, two CH 3-radicals and one H atom are bonded to AI atom, i.e. “asymmetric” structure. Since the different radicals are bonded to the AI atom, AI can be selectively and repeatedly deposited on Si surface. The precursor which has “asymmetric” structure is considered to have an important role for selective growth.

The Processing Windows for Selective Copper Chemical Vapor Deposition from Cu(hexafluoroacetylacetonate)trimethylvinylsilane

To identify the processing tolerance for the selective Cu chemical vapor deposition (Cu CVD) the processing windows were constructed with respect to deposition pressure and substrate temperature over thermally grown vs. various conducting substrates of W, , , , and Al. It is found that the width of selective deposition window decreases as the deposition pressure is increased, and no selective Cu deposition can be obtained as the deposition pressure exceeds 120 mTorr. The lowest temperatures for Cu CVD on various substrates including thermally grown, BPSG, TEOS, and PECVD were determined so that processing windows for selective Cu deposition on variously patterned wafers can be constructed. The selective Cu deposition was also conducted on patterned substrates with submicrometer feature sizes using the PECVD as the interlayer dielectric. The nucleation of Cu on the surface obviously acts as the major limitation for achieving selective Cu CVD. We postulate that the Cu containing adspecies, Cu(hfac), on the insulating surface may combine by surface diffusion, and these assembled adspecies then disproportionate by exchanging electrons with each other rather than transferring electrons through the substrate.

Catalytic synthesis of unsaturated nitriles from NO–alkane or NO–alkene on Pt–Sn/SiO2

The Pt–Sn/SiO2 catalysts prepared by selective bimetallic CVD reaction of SnMe4 with Pt particles on SiO2, characterized by EXAFS (extended X-ray absorption fine structure), yield acrylonitrile from NO + propene and methacrylonitrile from NO + isobutene and NO + isobutane with good selectivities, typically 70–93%, in contrast to negligible activity and selectivity (about one order of magnitude lower) with the monometallic Pt/SiO2 catalyst.

Selective Titanium Silicide for Industrial Applications

AbstractThe possibilities of using TiSi2 for contacts and interconnects in 0.25 μm and below design rule ICs are at present being investigated using the standard solid phase reaction (salicide) technique. Some problems still remain, such as phase transformation or dewettability over narrow lines. Over the last few years we have developed a TiSi2 selective CVD technique which is being used for 200 mm wafers in an industrial integrated cluster reactor. The system consists of two reaction chambers: one for Si epitaxy (and related alloys) and the other for TiSi2 deposition. The process sequence involves three main steps: (i) a wet chemical wafer cleaning, (ii) a selective silicon epitaxy for elevated source/drains to obtain minimum substrate consumption and (iii) the deposition of TiSi2 using the H2/SiH4 (or DCS)/TiCl4 gas system in the 650–750°C temperature range. The whole process time per wafer is shorter than 4 min. Selectivity, stoichiometric composition and resistivity of around 16 μmΩcm are obtained. The growth rate, uniformity, grain size and doping effects have been studied on single, polycrystalline, doped and undoped silicon. Device wafers have been used to compare the two processes, standard and CVD, obtaining electrical results such as lower series resistances, and a linewidth independent sheet resistance of down to 0.20 μm.

Influence of Wafer Preclean before Selective Tungsten CVD on Surface Properties of Interconnect and Intermetal Dielectric Materials

Results of selective tungsten CVD on titanium nitride (TiN) are summarized. The investigations are focused on the influence of precleaning and tungsten nucleation on the TiN and SiO2 surface, the CVD-W/TiN interface and the electrical properties of the contacts (via resistance). After a combination of HF dip and NF3 plasma a remarkable amount of fluorine was detected at the TiN surface which was not bound to Ti. This process showed the best effect on the reproducible nucleation of tungsten. No interfacial layer could be found by cross section TEM after the tungsten nucleation. But in the case of nucleations starting with SiH4 gas inlet tungsten growth begins with the formation of a mixture of α- and β-phase tungsten. More far away from the interface region only α-W was detected. The lowest via resistances in filled vias were measured for nucleations starting with WF6 gas inlet. For introducing SiH4 first the via resistance could be decreased using a H2 plasma conditioning of the wafer in the deposition chamber after dry pretreatments. For this case no remarkable change of the deposition surface was found by XPS. At wafers pretreated with BCl3/N2 plasmas on both surfaces (TiN and SiO2) boron nitride was found.

Large scale two-step selective aluminum CVD on laser patterned palladium lines

In the present report we first outline and characterize the details of uniform deposition of PdAc from an acetone solution on a large area. Then, we investigate the parameters that highly influence the thickness and quality of the laser direct-written palladium lines (spin coating speed among others). Currently, good quality and uniform patterning of laser written thin lines of Pd have been achieved on samples as large as 4 inches in diameter. The Pd lines are well resolved (minimum of 3 μm in width now) and exhibit fairly good resistivity around 30 μΩ⋯cm. They also showed good adhesion to the SiO 2 substrate as they endure repeated Scotch tape adhesion tests. Moreover, the second step of highly selective Al-CVD has been investigated under various conditions and gave rise to resistivities of about 6.5 μΩ⋯cm and 3000 Å thickness for a 7 min deposition. This process stands out as very promising for packaging and high density interconnect technologies.

A Thermodynamic Analysis of Selective Area CVD of Titanium Nitride Compound by the Alternating Cyclic Method

As the first step in investigating the selective area chemical vapor deposition of titanium compounds, which are of considerable interest in semiconductor technology, a thermodynamic analysis has been performed for the selective area chemical vapor deposition of titanium nitride, over an extensive temperature, pressure, and composition range, using the alternating cyclic (A.C.) process. In this approach deposition via the hydrogen reduction of is followed cyclically by the etching of spurious nuclei from mask regions via an embedded disproportionation reaction. The thermodynamic calculations have been set up using a first principles analysis, and carried out via the computer program, SOLGASMIX, which is based on the minimization of the system's Gibbs free energy. The first principles constraining conditions and the equilibrium constant constraining equations have then been employed as integrity checks of the outputs of the computer program. In addition, using the first principles approach, solid‐vapor solubility curves have been derived for the cases examined. These calculations have indicated that the selective deposition of by this novel method is feasible and have defined the parameter space in which to conduct the selective area deposition in A.C. fashion.

SiGe drift base bipolar transistor with self-aligned selective CVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 /spl Omega/ (emitter area: 0.2/spl times/3 /spl mu/m/sup 2/), and an f/sub MAX/ of 37.1 GHz is achieved by employing 0.2-/spl mu/m EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Selective Copper Cvd on Diamond Surfaces Using Self-Assembled Monolayers

ABSTRACTSelective chemical vapor deposition (CVD) of conductive, adherent copper films was achieved on single-crystal and polycrystalline diamond substrates modified with a ligating aminosilane and a Pd-based catalyst. Only isolated copper particles deposited on hydrogenated or aminosilane-coated diamond substrates without Pd. The Pd catalyst enhanced selectivity by a factor of 103 to 104. Copper CVD was performed in a cold-walled chamber at 446-456 K and 8x10-3 Pa using hexafluoroacetylacetonate-Cu-trimethylvinylsilane in H2 (1:1). Surfaces were characterized with x-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). Patterned Cu features were formed by exposing the aminosilane films to patterned ultraviolet (193 nm) radiation prior to Pd-catalyst addition and Cu CVD.

Interface reactions between CVD and PVD tungsten and aluminium

Selective tungsten CVD on aluminium offers the opportunity to realize reliable contacts (via fill) for submicron multilevel metallizations. CVD tungsten depositions directly on Al (1% Si) and on a sputtered tungsten glue layer on top of the aluminium were investigated. The interfaces of CVD-W/Al and PVD-W/Al are of special interest because of their influence on contact resistance and stability of the interconnect. The interfaces were examined by cross section TEM and additionally by energy-dispersive X-ray spectroscopy (EDX) and AES depth profiling of thin blanket deposited tungsten layers. Intermediate layers were found at both interfaces. An amorphous Al-F compound was detected at the interface of CVD-W deposited by silane reduction of WF 6 and AlSi. At the PVD-W/AlSi interface a crystalline intermetallic compound of W and Al can form depending on the thermal treatment. Such an interlayer was found already after annealing twice at 400°C for 30 min. A diffusion of aluminium into tungsten was proved in all investigated layer combinations. The diffusion depth depends on thermal treatment and on the structure of the tungsten layer.

Selective tungsten CVD on sputtered tungsten for via fill

Selective tungsten CVD for via filling was investigated using a sputter-deposited tungsten top layer on aluminium as glue layer. A single wafer R & D CVD equipment with load lock, plasma process capability, thermostatable reactor walls and a simple gas inlet was used for this purpose. The influence of wafer history, different wafer pretreatments and deposition parameters on tungsten growth and loss of selectivity (LOS) was examined in the WF 6-SiH 4-H 2 system. Chamber conditioning was carried out by a NF 3 and following H 2 plasma. A short in situ NF 3 plasma was found as a promising wafer pretreatment providing good nucleation conditions for selective tungsten depositions. At wafer temperatures of about 225°C and total pressures of 33 Pa vias down to 0.3 μm and with a depth of 1 μm were filled without loss of selectivity. Deposition rates greater than 400 nm/min were reached.

Adhesion and leakage current characteristics of selective CVD tungsten films on the silicon substrate

In this study we investigated the effects of SF 6 and CF 4 plasma pretreatments on the adhesion and junction leakage characteristics of the selective CVD W films by SiH 4 reduction of WF 6 on the Si substrate. The SF 6 plasma pretreatment performed in situ prior to W deposition to remove the polymer films in contact holes results in enhacement of the adhesion of W films to the Si substrate but degradation of junction leakages due to vertical and lateral Si consumptions. The CF 4 plasma pretreatment performed as the last step of the reactive ion etching for contact window opening produced the W/Si contacts of good adhesion, low contact resistances and low junction leakages for thin W films, while it produced the W/Si contacts of poor adhesion and high contact resistances fir thick W films. The selective CVD W films deposited by the three step process of SiH 4 reduction/in situ annealing/SiH 4 reduction was found to have both good adhesion and low junction leakage characteristics

Silicides for Highly Integrated Memory and Logic Circuits

ABSTRACTState of the art DRAM and logic processes widely make use of silicides formed by refractory metals like Ta, Mo, W, Ti, Co, or others. The methods for silicide formation range from sputtering, reaction with predeposited metal, to selective CVD deposition.The most common application of silicides in state of the art CMOS processes is to use them as a conducting layer that can withstand high temperature processes and that has a significantly lower sheet resistivity than doped mono or poly crystalline silicon. Besides their role as a temperature stable conductor silicides have further interesting properties when using them as a diffusion source for impurities to generate shallow junctions, or as an alternative gate material with a work function in the middle of the silicon band gap.Based on the example of the self aligned silicidation with titanium silicide the limitations of the state of the art technology will be shown and requirements for future applications will be discussed.

Predictive Surface Kinetic Analysis: The Case of TiSi2 CVD

Recently, TiSi2 has been the object of considerable study because of its low resistivity among the transition metal silicides and its compatibility with existing ULSI technology [1,2]. Film growth by CVD offers the potential for selective area deposition and high production throughput. However, selective CVD of TiSi2 from gas phase SiH4 and TiCl4 is usually accompanied by a competing reaction which consumes intolerable amounts of the Si substrate [3,4]. Controlling this consumption is crucial in TiSi2 growth; however, no quantitative correlation exists between silicon consumption and growth conditions or film thickness. Additionally, the reaction mechanism for TiSi2 growth is poorly understood, and some disagreement even exists about the reaction stoichiometry [5,6]. The combined CVD/UHV approach we have developed fills many gaps in the current understanding of TiSi2 CVD.

New routes to Cu‐patterned teflon substrates

In microelectronics, copper conductors and Teflon substrates are the materials of choice in many applications due to the high conductivity of copper and the low dielectric constant of Teflon. The nature of Teflon, however, results in low adhesion strength, which makes a multi‐step Cu‐deposition process necessary. Here, an alternative, selective CVD, which can produce smaller feature sizes and reduces the need for wet etching, is presented and explained.

Preparation of Cu Thin Films by the Decomposition of Copper Acetylacetonate on Catalytically Active Substrate Surfaces

Abstract A selective CVD system used to deposit the central metal of a volatile complex preferentially on catalytically active substrate surfaces was examined. Copper(II) acetylacetonate was vaporized in a flow of hydrogen and decomposed on Ni, Pd, and Al plates in order to deposit metallic copper. When a Ni plate was used as the substrate, deposition of metallic copper occurred at temperatures in the range 13O–180 °C only on the substrate surfaces. The formation of an ultrathin film of Cu of uniform thickness was confirmed. On a Pd substrate, the formation of an ultrathin Cu film of uniform thickness was also observed. On an Al substrate, however, deposition occurred nonselectively at temperatures above 160 °C, not only on the substrate surface, itself, but also on the wall of the glass tube as well as the quartz wool surrounding the Al plate. In addition, the formation of fine particles of Cu, instead of thin film, was found to exist on the substrate. Because the deposition of Cu took place on catalytically active surfaces selectively, the deposition was considered to proceed by a catalytic hydrogenation of the C=O bond of the ligand, thus detaching it from the Cu ion and allowing it to decompose the complex and deposit Cu metal.

Selective Aluminum CVD for Sub-Micron VIA Plug Filling

ABSTRACTWe present a novel technique to metallize high-aspect-ratio, small-dimension contact holes and via plugs for application to integrated circuits and packaging. The technique uses a laser-assisted process to deposit a thin film of aluminum from DMA1H, which forms a seed layer for subsequent selective CVD. The resistivity of the deposited aluminum is nearly that of the bulk metal, the contact resistivity is good (∼0.03 μΩ-cm2), and the morphology of the deposited film is comparable to that obtained with physical vapor deposition. This process has been used to fill via holes in a SiO2 substrate, and small-diameter (0.7 μm), high-aspect-ratio (3:1), aluminum plugs have been repeatedly formed without the incorporation of voids. A custom-made via chain structure was used to determine the via resistance (plug and contact), which was found to be 0.1 -0.3 Ω. Our technique opens a new process window for void-free high-aspect-ratio via and contact hole filling, and is particularly interesting in that it offers the potential to use aluminum or aluminum-copper in plug metallization.

Electromigration characteristics of tungsten plug vias under pulse and bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000*) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions ( 10 kHz). The results are in agreement with the vacancy relation model. >