ΣΔ Modulator Research Articles

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators

On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators

A Novel Approach for Realizing Loop-Filter in Low-Distortion Noise-Coupled ΣΔ Modulators

This paper presents an innovative general structure for a single-loop Sigma-Delta ([Formula: see text]) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6[Formula: see text]dBFS and a sampling frequency of 2.56[Formula: see text]MHz, the signal to noise plus distortion (SNDR) was 81.9[Formula: see text]dB, and the dynamic range (DR) was 88[Formula: see text]dB for a 20[Formula: see text]KHz bandwidth. The modulator’s power consumption was 126.9[Formula: see text][Formula: see text]W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

A Low-Distortion Low-Power MASH Architecture ΣΔ Modulator with Double-Sampling

This paper presents a low-distortion and low-power multi-stage noise-shaping (MASH) architecture Sigma-Delta ([Formula: see text] modulator with double-sampling. The modulator uses a cascade of integrator feed-forward (CIFF) structure as a cascaded modulator in a MASH architecture. Since the CIFF structure provides a feedforward path from the input signal to the quantizer, the input signal is directly transmitted to the output without loop processing, relaxing the linearity requirement of the modulator, reducing performance requirements for the OTA and harmonic distortion. Double-sampling technique is adopted in the first integrator to double the sampling rate, improving the accuracy of the modulator without the increase of power consumption. In order to eliminate the influence of capacitor mismatch in the sampling network, a fully floating differential switched capacitor (SC) feedback digital-to-analog (DAC) is used in the integrator. The simulation results show that the [Formula: see text] modulator achieves 113[Formula: see text]dB signal-to-noise and distortion ratio (SNDR) and the power consumption is 3.15[Formula: see text]mW from a 5[Formula: see text]V power supply.

Analysis and design of a fourth-order ΣΔ ADC for MEMS digital gyroscope sensors

This paper presents a fourth-order sigma-delta (ΣΔ) ADC applied to a micro-electro-mechanical system (MEMS) gyroscope system. First, a system-level model of ΣΔ modulator containing non-ideal factors is established, and the optimal system performance of the ΣΔ modulator is determined by optimizing the feedforward path and the feedback coefficient of the feedback path. Then, the operational transconductance amplifier (OTA) with chopping technique and clock timing to control bias current in the first stage integrator of the circuit design is able to reduce not only the flicker noise of the modulator, but also reduce the system power consumption. Third, the design of other essential circuit modules is presented, and the circuit performance meets the requirements and low-power consumption is achieved. The designed ΣΔ ADC uses a 0.18 μm CMOS BCD process, with a ΣΔ modulator area of 0.64 mm2 and a digital filter area of 2.03 mm2. When the sampling frequency is 2 MHz and the signal bandwidth is 7.8 kHz, the experimental measurement results show that the proposed ΣΔ modulator with the fourth-order CIFF structure can achieve a signal-to-noise ratio (SNR) of 66.3 dB and an effective number of bits (ENOB) of 10.07 bits, with a dynamic range (DR) of 89 dB and a power consumption of 9 mW. The SNR of ΣΔ ADC after filtering is 63 dB, which meets the requirements of high DR and low-power consumption of MEMS digital gyroscope sensors.

A Low-Noise Interface ASIC for MEMS Disk Resonator Gyroscope.

This paper proposes a low-noise interface application-specific integrated circuit (ASIC) for a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) which operates in force-to-rebalance (FTR) mode. The ASIC employs an analog closed-loop control scheme which incorporates a self-excited drive loop, a rate loop and a quadrature loop. A ΣΔ modulator and a digital filter are also contained in the design to digitize the analog output besides the control loops. The clocks for the modulator and digital circuits are both generated by the self-clocking circuit, which avoids the requirement of additional quartz crystal. A system-level noise model is established to determine the contribution of each noise source in order to reduce the noise at the output. A noise optimization solution suitable for chip integration is proposed based on system-level analysis, which can effectively avoid the effects of the 1/f noise of the PI amplifier and the white noise of the feedback element. A performance of 0.0075°/√h angle random walk (ARW) and 0.038°/h bias instability (BI) is achieved using the proposed noise optimization method. The ASIC is fabricated in a 0.35 μm process with a die area of 4.4 mm × 4.5 mm and power consumption of 50 mW.

Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Defined Radio

This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-ΣΔM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals.

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals.

Digital and smart sensors are commonly implemented using multi-bit Modulators. Undesired signals can be present at the ADC input, such as low-frequency signals with medium or high amplitude, as a consequence of mechanical artifacts in the MEMS and/or temporary signal overload. Simulations and measurements of those sensors with such signals show temporary increments of in-band noise power. This paper investigates the factors that produce this transient performance loss. Interestingly, noise increments happen when the modulator is forced to toggle between three adjacent levels and is not correlated with the typical tonal behavior of Modulators. Hence, the sensor performance is sensitive to some specific input patterns even if tonal behavior is decreased by dithering the input of the ADC. Different error sources, such as the mismatch between DAC cells, loop filter linearity error, and quantization error, contribute to the observed noise increments. Our aim is to analyze each of these error sources to understand and quantify in-band noise power increments, and to desensitize the ADC from the undesired input patterns. Some estimation equations are proposed and verified through extensive simulations, by means of deterministic and stochastic methods. These equations are influenced by some modulator parameters and can be used to optimize them in order to reduce such in-band noise power increments.

New 2 2 Sigma Delta Modulators for Different Applications

This work presents the design of a new 2-2 programmable sigma delta modulator architecture, for different applications, this transformation design of the ΣΔ modulator low-pass, band-pass and high-pass or vice versa with loopbacks addition, which improved the linearity of the converter and reduced the quantization noise. In this work, the MASH structure enables the implementation of stable and high-order modulator. This makes low voltage and low power applications ideal. The simulation result for sigma delta modulator for biomedical applications exhibit a signal to noise ratio is 95 dB @ 250Hz bandwidth and a 75dB @ 200KHz ,85dB @1MHz for pass band modulator. The SNR is about 70dB for 5MHz bandwidth and for high pass application. This tool will allow a development contribution and characterize a system optimization set from the start while remaining at a high level of design that is suitable for electronic systems and models VHDL-AMS, RF, Biomedical.

A 101 dB SNR fourth-order ΣΔ modulator for MEMS digital geophones

A fourth-order ΣΔ modulator (SDM) applied for micro-electro-mechanical systems (MEMS) digital geophones is presented in this paper. At the system stage, the proposed fourth-order SDM adopts a hybrid path technology including a feedforward path and a feedback path. At the design stage, a class AB operational transconductance amplifier with a gain bootstrap structure and chopper technique is employed in the first-stage integrator, which can achieve high DC gain, GBW, (Slew Rate) SR and reduce flicker noise, ensuring high (Signal-to-Noise Ratio) SNR for the proposed SDM. Meanwhile, other key modules are designed to meet basic requirements and achieve low power consumption at the same time. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and its final area is 3.09 mm2. When the sampling frequency of 512KHz and signal bandwidth of 2KHz are adopted, the measured results show that the proposed fourth-order SDM can achieve SNR of 101 dB and ENOB of 16.4 bits with less than 5mW power consumption, which meet the requirements of high dynamic range and low power in MEMS digital geophones.

Analysis and Design of Low-Complexity Stochastic DEM Encoder for Reduced-Distortion Multi-bit DAC in Sigma-Delta Modulators

A low-complexity stochastic dynamic element matching (DEM) technique to mitigate the distortions caused by the nonlinearity of multi-bit digital-to-analog converters (DACs) in sigma-delta modulator is proposed. Multi-bit DAC noise is analyzed in detail from a signal processing point-of-view in this research, and then implementation of the basic stochastic unit named swapper cell which includes bar state and cross state controlled by a 1-bit pseudo-random noise signal, is illustrated. To reduce the hardware complexity, a multi-layer scheme for multi-input multi-output stochastic encoder is presented and demonstrated based on rigorous mathematical derivation. For a n-input n-output version, the number of the switch elements employed in the proposed encoder is reduced to 2nlog2n from the conventional n!. Simulation results show that, with the use of the stochastic encoder, severe harmonic distortions resulted by the DAC elements mismatch errors are suppressed effectively. When the proposed encoders are applied to the internal multi-bit DACs in sigma-delta (ΣΔ) modulators, large improvements of the linearity performance of the modulators are achieved. Additionally, the analyses and explanations for this stochastic scheme provide a theoretical foundation for the future development of noise shaping DEM.

An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems.

This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.

A fractional-order zero-phase integrator for sigma-delta modulator

In the system of MEMS digital geophone, the mechanical sensing element and post-stage detection circuit are combined to work as the Sigma-Delta (ΣΔ) modulator. The performance of ΣΔ modulator can be improved by cascading electrical integrators behind the sensitive structure. Thus, additional integrators are introduced in series with the mechanical sensing element to form the high order ΣΔ modulator. In fact, the increase of the system order of ΣΔ modulator is limited to maximum 5 or 6 order due to the system instability. In other words, the stability of ΣΔ modulator system will be weaken caused by the phase loss from the additive integrators. This paper proposes a fractional-order zero-phase integrator (FOZPI) that in series with the 5th-order ΣΔ modulator to effectively suppress the phase distortion in the noise-shaping process for MEMS digital geophone. The proposed ΣΔ modulator with the FOZPI applies in MEMS digital geophone can better enhance the compromise capability between the high signal to noise ratio (SNR) and strong robust stability than the pure 5th-order ΣΔ modulator does. The order of FOZPI is designed by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameter and further improve the noise performance. Finally, the simulation results show that the proposed ΣΔ modulator with FOZPI scheme is an effective way to improve the performance and loop stability for ΣΔ modulator.

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital ΣΔ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.

A High-Performance Digital Interface Circuit for a High-Q Micro-Electromechanical System Accelerometer.

Micro-electromechanical system (MEMS) accelerometers are widely used in the inertial navigation and nanosatellites field. A high-performance digital interface circuit for a high-Q MEMS micro-accelerometer is presented in this work. The mechanical noise of the MEMS accelerometer is decreased by the application of a vacuum-packaged sensitive element. The quantization noise in the baseband of the interface circuit is greatly suppressed by a 4th-order loop shaping. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a 4th-order Sigma-Delta (ΣΔ) modulator. The stability of high-order ΣΔ was studied by the root locus method. The gain of the integrators was reduced by using the proportional scaling technique. The low-noise front-end detection circuit was proposed with the correlated double sampling (CDS) technique to eliminate the 1/f noise and offset. The digital interface circuit was implemented by 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. The high-performance digital accelerometer system was implemented by double chip integration and the active interface circuit area was about 3.3 mm × 3.5 mm. The high-Q MEMS accelerometer system consumed 10 mW from a single 5 V supply at a sampling frequency of 250 kHz. The micro-accelerometer system could achieve a third harmonic distortion of −98 dB and an average noise floor in low-frequency range of less than −140 dBV; a resolution of 0.48 μg/Hz1/2 (@300 Hz); a bias stability of 18 μg by the Allen variance program in MATLAB.

High accuracy frequency extraction based on sigma-delta ADC applied in resonant dew point sensor

One of the design challenges for the resonant dew point measurement was optimizing the rapidity and accuracy of frequency extraction to meet the requirements. We have developed a 1-bit second-order sigma-delta (ΣΔ) analog-to-digital (ADC) to be applied in it, which was anticipated to have a highest resolution and design flexibility than traditional ADC. Based on the Butterworth filter, the design of ΣΔ modulator was modeled firstly to evaluate the performance of filters scheme before the hardware implementation. Furthermore, the design and implement of the digital decimation filters was presented to extend the design flexibility and application. To improve the accuracy and instantaneous of frequency estimation, we developed a new frequency estimation algorithm, which combined the Fast Fourier transform (FFT) and the chirp-Z transform. We built a complete hardware implementation system. We tested the performance of the designed ΣΔ ADC and found that has 11-bit resolution and the high flexibility. The experiment results showed the root mean square (RMS) error of frequency estimation was 0.0917 Hz with minimum error 0.01 Hz, and the SNR can achieve 123.04 dB. Results showed the proposed frequency estimation error decreases approximately 35 times under the premise of the same computation with FFT. Moreover, every completion of the frequency estimation only takes less than 1 s. Finally, the experiment of dew point measurement was carried out. The results indicated that the proposed measurement system was feasible for the frequency extraction of the resonant dew point sensor.

Digital platform for Sigma-Delta accelerometer assessment and test

A digital platform for fast assessment and testing of multiple order architectures of electromechanical Sigma-Delta modulators for MEMS capacitive accelerometers is introduced in this paper. It is well known that the introduction of a negative feedback loop on sensors presents significant advantages to improve important characteristics, such as precision, linearity, speed, and dynamic range over open-loop operation (Borovic et al. in J Micromech Microeng 15(10):1917–1924, 2005; Chen et al. in IEEE Sens J 16(17):6476–6495, 2016). In a closed-loop system, the controller is responsible for the aforementioned improvements, enabling the relaxation on the manufactured device specifications. Consequently, it demands better and more complex electronic circuits for the controller. A configurable multi-order (2nd, 3rd, 4th and 5th) ΣΔ module was developed in field-programmable gate array, along with the necessary signal acquisition and actuation modules, using a processor-centric approach, ensuring real-time performance, simple reconfiguration, and fast assessment of different orders and gains for the ΣΔ modulator with real MEMS devices. The system is capable of a measuring cycle lower than 100 ms. The platform was used to perform a comparison between two different types of MEMS accelerometers, evaluating the results obtained with second, third, fourth and fifth modulation orders for two bandwidth values—200 and 1000 Hz. The best noise figure achieved was 4.4 µg/√Hz, using a fifth order ΣΔ modulator and the device with the larger seismic mass. A comparison between three similar devices is also performed, as well as a comparison between simulated and experimental results.

Study of closed-loop high-resolution sigma-delta for a MEMS accelerometer

In this paper, a high-resolution Sigma-Delta (ΣΔ) modulator in a standard 0.5 µm CMOS technology for a MEMS accelerometer is presented. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a back-end forth-order Sigma-Delta modulator. The low-noise front-end detection circuit is proposed with correlated double sampling (CDS) technique to eliminate the 1/f noise and offset of operational amplifier. The capacitance compensation array is used for rejecting the sensor element mechanical offset. The lead compensator circuit is to ensure the stability of the high-order closed-loop system. The interface is fabricated in a standard 0.5 µm CMOS process and the active circuit area is about 8 mm2. The MEMS accelerometer system consumes 25 mW from a single 7 V supply at a sampling frequency of 250 kHz. The ΣΔ modulator can achieve an effective number of bits 20.30 bits and an average noise floor in low-frequency range of 140 dB.

Modeling and Analysis of a Closed-Loop System for High-Q MEMS Accelerometer Sensor

High-Q sensing element is desirable for high performance while makes the loop control a great challenge. This paper presents a closed-loop system for high-Q capacitive MEMS accelerometer which has achieved loop control effectively. The proportional-derivative(PD)control is developed in the system to improve the system stability. In addition, pulse width modulation (PWM) electrostatic force feedback is designed in the loop to overcome the nonlinearity. Furthermore, a sigma-delta (ΣΔ) modulator with noise shaping is built to realize digital output. System model is built in Matlab/Simulink. The simulation results indicate that equivalent Q value is reduced to 1.5 to ensure stability and responsiveness of the system. The effective number of bits of system output is 14.7 bits. The system nonlinearity is less than 5‰. The equivalent linear model including main noise factors is built, and then a complete theory of noise and linearity analysis is established to contribute to common MEMS accelerometer research.

A closed-loop ΣΔ modulator for micromechanical capacitive sensors

This paper describes a CMOS fully-differential switched-capacitor (SC) single-loop Sigma-Delta (ΣΔ) modulator specialized for highly precise micromechanical capacitive sensors. This design adopts a single-loop, fourth-order, one-bit quantization architecture with feedforward paths for lower nonlinearities and power consumption. Systematic optimization is used to avoid deterioration in conversion accuracy caused by capacitor mismatch. Chopper-stabilization and double-sampling techniques are also employed to enhance performances in noise depression. Manufactured in a standard 0.35 µm CMOS process, the ASIC occupies an area of 5.32 mm2 including 25 pads. This modulator achieves a signal-to-noise ratio (SNR) of 105.2 dB and dynamic range (DR) of 113.7 dB. The whole chip consumes 12.6 mW from a 5 V supply.