ΣΔ Modulator Research Articles

A Fully Integrated CMOS Fluorescence Biochip for DNA and RNA Testing.

Design and successful implementation of a fully-integrated CMOS fluorescence biochip for DNA/RNA testing in molecular diagnostics (MDx) is presented. The biochip includes a 32×32 array of continuous wave fluorescence detection biosensing elements. Each biosensing element is capable of having unique DNA probe sequences, wavelength-selective multi-dielectric emission filter (OD of 3.6), resistive heater for thermal cycling, and a high performance and programmable photodetector. The dimension of each biosensor is 100µm×100µm with a 50µm×50µm Nwell-Psub photodiode acting as the optical transducer, and a ΣΔ modulator based photocurrent sensor. The measured photodetector performance shows ~116 dB detection dynamic range (10fA - 10nA) over the 25°C - 100°C temperature range, while being ~1 dB away from the fundamental shot-noise limit. To empirically demonstrate the compatibility of this biochip with MDx applications, we have successfully utilized the array and its thermal cycling capability to adopt a 7-plex panel for detection of 6 human upper respiratory viruses.

Impulsive Sound Detection Directly in Sigma-Delta Domain

Abstract Recent implementations of Sigma-Delta (ΣΔ) converters have achieved low cost, low power consumption, and high integration while maintaining resolution as high as in Nyquist-rate converters. However, its usage implies demodulating the source signal delivered from ΣΔ modulation to Pulse-Code Modulation (PCM) on a pre-processing stage. This work proposes an algorithm based on Discrete Cosine Transform for impulsive signal detection to be applied directly on a modulated ΣΔ bitstream, targeting to reduce computational cost in acoustic event detection applications such as gunshot recognition systems. From pre-recorded impulsive sounds in ΣΔ format, it has been shown that the new method presents a similar error rate in comparison with traditional energy-based approaches in PCM, meanwhile, it reduces significantly the number of operations per unit time.

A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage

A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a third-order filter implemented with a lossless integrator and a multiple-feedback single-amplifier biquadratic filter with embedded loop stability compensation. An active summing block is implemented by employing a common-gate current buffer followed by a transimpedance amplifier. This combination relaxes the specification requirements of the operational amplifier by making its required BW independent of the closed-loop gain. The proposed technique achieves optimum BW with reduced power consumption, making it functional for over gigahertz operation. Fabricated in a standard 40-nm CMOS technology, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise-and-distortion ratio of 65.5 dB over 75-MHz BW while consuming 22.8 mW of power. The obtained Walden's figure of merits is 98 fJ/conv-step.

4th order capacitively-coupled LC-based [formula omitted] modulator

In this paper, we present the design and implementation of an RF bandpass ΣΔ modulator where the loop filter is a 4th order capacitively-coupled LC filter. A design methodology using coupling capacitor and the feedback Finite Impulse Response Digital-to-Analog Converter (FIRDAC) coefficients in order to obtain the desired Noise Transfer Function (NTF) is presented. The proposed capacitively-coupled bandpass LC ΣΔ is implemented in a 130nm CMOS process. The fabricated chip, operating under a supply voltage of 1.2V, has a varying center frequency range of 400–442MHz with a corresponding sampling frequency range of 533–589MHz. A maximum Signal-to-Noise Ratio (SNR) of 50dB in a 4.5MHz bandwidth for a power consumption of 20mW was achieved. The effect of the clock jitter on the Analog-to-Digital Converter (ADC) performance is measured and presented.

<inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$</tex-math> </inline-formula> Effects and Charge Locking in Capacitive MEMS Under Dielectric Charge Control

This work investigates, analytically and experimentally, the effects induced by the use of a first-order sigma-delta (ΣΔ) feedback loop as a control method of dielectric charging for capacitive microelectromechanical systems (MEMS). This technique allows setting of a desired level of net charge in the dielectric of a MEMS device by continuously alternating the polarity of the actuation voltage. This control system displays a number of interesting effects, inherited from ΣΔ modulation and not usually found in conventional MEMS applications, with the charge-locking phenomenon being the most relevant. The convergence time and the effectiveness of the control method are also investigated and discussed.

A Reconfigurable 4 th Order ΣΔ Modulator with a KT/C Noise Reduction Circuit

A Reconfigurable 4 th Order ΣΔ Modulator with a KT/C Noise Reduction Circuit

MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage

In this paper, a multi-stage noise-shaping (MASH) sigma-delta (ΣΔ) modulator is proposed to be used in low oversampling ratio (OSR) applications. It utilizes a noise-shaped two-step (NSTS) analog-to-digital converter (ADC) in the second stage and benefits its inter-stage gain to provide an extra attenuation of the quantization noise such that the same specifications of a traditional modulator are achieved but with a lower order of noise-shaping. Furthermore, large number of bits is resolved in the second stage while equal number of comparators is used. Compared to the single-loop NSTS ADC, in the proposed structure, the complexity problem of the feedback path and coefficient spreading are eliminated. As an example, a MASH 2-1 sigma-delta modulator has been designed and simulated in a 90nm CMOS process using Spectre. The achieved resolution is 13.44 effective number of bits in 6.25MHz signal bandwidth while consuming 19.6mW power from a single 1V supply. The sampling frequency is 100MHz and the simulated figure of merit is 141 fJ/conv-step which shows the efficiency of the proposed modulator.

System-Level Power Optimization of Digital Audio Back End for Hearing Aids

This work deals with power optimization of the audio processing back end for hearing aids--the interpolation filter, the sigma-delta ($$\Sigma \Delta )$$ΣΔ) modulator and the Class D power amplifier (PA) as a whole. Specifications are derived, and insight into the trade-offs involved is used to optimize the interpolation filter and the $$\Sigma \Delta $$ΣΔ modulator on the system level so that the switching frequency of the Class D PA--the main power consumer in the back end--is minimized. A figure-of-merit which allows judging the power consumption of the digital part of the back end early in the design process is used to track the hardware and power demands as the trade-offs of the system-level parameters are investigated. The result is the digital part of the back end optimized with respect to power which provides audio performance comparable to state-of-the-art. A combination of system-level parameters leading to the lowest switching frequency of the Class D power amplifier reported in the literature for the $$\Sigma \Delta $$ΣΔ modulator-based back end is derived using this approach.

Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators

In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta ($$\varSigma \varDelta$$ΣΔ) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order $$\varSigma \varDelta$$ΣΔ modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.

EDA tools for designing ΣΔ modulators working in the currentmode

EDA tools for designing ΣΔ modulators working in the currentmode

A Simple Structure for MASH $$\Sigma \Delta $$ Σ Δ Modulators with Highly Reduced In-Band Quantization Noise

A new topology of multi-loop sigma-delta $$(\Sigma \Delta )$$(ΣΔ) modulators is proposed which utilizes two analog inter-stage paths to improve the noise-shaping ability of the modulator by one order and simultaneously optimizing one pair of noise transfer function zeros. Furthermore, an improved version of this modulator is presented which is simpler to implement. So, by using minimum extra circuit and without increasing the number of active blocks, the in-band quantization noise is significantly reduced, and hence, the modulator signal-to-noise and distortion ratio (SNDR) is highly increased. As an example, a multistage noise-shaping (MASH) 2-1 $$\Sigma \Delta $$ΣΔ modulator based on the improved proposed structure is more examined. Some implementation considerations including the timing issue and first-stage quantization noise extraction are verified. Theoretical analysis and simulation results in both system and circuit levels are presented to confirm the usefulness of the proposed structure. The modulator is implemented in a 90-nm CMOS technology using Spectre-RF. For 10 MHz signal bandwidth, 85.2 dB SNDR and 87 dB dynamic range are achieved, while the power consumption is 31.6 mW from a single 1 V power supply.

Continuos Time ΣΔ modulator with efficient gain compensated integrators

This paper presents the design of a second-order continuous time (CT) ΣΔ modulator with DC gain compensated OTA based integrators. Compared to similar solutions, this novel technique uses a simple transconductor stage to compensate for the multi-bit feedback DAC inputs in the modulator. The work details the effective compensation technique by using a negative transconductance stage that only increases a 17% of the overall ΣΔ power consumption. The compensated CT modulator is implemented in a 65nm CMOS process and achieves a SQNR of 79.3dB and a state-of-the-art FoM of 31fJ/conv-level.

Design, simulation, and implementation of an integrated, hybrid photocurrent-to-digital converter in CMOS technology

This article presents a design, modeling, simulation, and measurements of a hybrid photocurrent-to-digital converter integrated together with photo-diodes in a 130nm CMOS process, without any additional process steps. Photo-currents of integrated photo-diodes with different responsivities to different wavelength of the light and light intensity are converted into 22-bits digital results in 2ms. The results can then be converted into CIE XYZ or RGB color luminosity space using dedicated DSP algorithm. A high resolution, hybrid, ADC converts light induced photo-currents into 22-bit digital results, canceling the dark current of the photodiodes and 1/f noise and offset voltage of the input stage of the modulator. The whole converter consumes on average less than current at supply voltage at 10 conversions per second. It occupies approx. 0.8mm2 of silicon area, including the three photodiodes, a multiplexer, and the ΣΔ modulator.

A 106 dB A-Weighted DR Low-Power Continuous-Time <inline-formula> <tex-math notation="LaTeX">$\Sigma \Delta $</tex-math> </inline-formula> Modulator for MEMS Microphones

This paper presents a low-power, high-performance continuous-time ΣΔ modulator for MEMS microphones frontend. The ΣΔ modulator 3rd-order loop filter has been implemented with a low-noise, power-optimized active-RC architecture that uses only two operational amplifiers. This solution, along with the use of a 15-level quantizer and of a feedback DAC with three-level current-steering elements, which minimizes the noise contribution for small input signals, allows achieving a DR larger than 100 dB, while consuming less than 0.5 mW, as required in always-running audio modules for portable devices. The proposed ΣΔ modulator, realized in 0.16 μm CMOS technology with an area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieves 106 dB A-weighted DR and 91.3 dB peak SNDR, consuming 390 μW from a 1.6 V power supply.

Power and area efficient continuous time ΣΔ modulator based on local feedback

This paper presents an area efficient implementation of a second order continuous time (CT) sigma-delta (ΣΔ) modulator. In the proposed implementation, traditional operational amplifiers (op-amps) have been replaced by a low-complexity current mode structure based on local feedback to obtain power and area efficiency. The ΣΔ modulator specifications have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main goals of the presented design. Experimental results show 8.75 bits of Effective-Number-Of-Bits (ENOB) in a 25kHz signal bandwidth with only 3.8μW of power consumption operating at 1.7V of supply voltage. A Figure Of Merit (FOM) of 175 fJ/level has been achieved with total area occupancy (without pads) of 150μm×125μm in a 0.35μm CMOS technology.

An Enhanced Light-Load Efficiency Step Down Regulator with Fine Step Frequency Scaling.

This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based controller, while light load efficiency is realized through the introduction of fine step frequency scaling (FSFS) which continuously adjusts the switching frequency of the converter with load conditions. Regulation efficiency is further improved by adoption of mode hopping (continuous conduction mode (CCM)/discontinuous conduction mode (DCM)) and utilization of a fully digital implementation. Furthermore, the presented converter maintains low output voltage ripple across its entire load range by reconfiguring the ΣΔ modulator's quantization step and introducing dither to the loop filter. The proposed modulator was implemented in 14nm bulk CMOS process and validated with post layout simulations. It attains a peak efficiency of 95% at heavy load conditions and 79% at light loads with a maximum voltage ripple of 15mV at light loads.

A Compact First-Order Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

On complex system-on-chips (SOCs), a compact on-die analog-to-digital converter (ADC) is required in high-volume testing, in order to reduce the test time and improve the test coverage of on-die analog intellectual properties (IPs). This paper presents a compact first-order ΣΔ modulator for on-die voltage measurements in such applications. The primary design focus is to achieve a highly compact area so that many instances can be integrated to cover the testing of multiple analog IPs on a single chip die. The proposed modulator deploys an inverter-based architecture which enables the aggressive area reduction. There are two new additional enhancements: 1) hardware dithering to minimize the limit-cycling effect and 2) time-multiplexed pseudodifferential operation for common mode rejection. The modulator exhibits a figure of merit (FOM) of 554.7 fJ/conv-step, in spite of the compact area of only 0.00023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Adjustable Nyquist-rate System for Single-Bit Sigma-Delta ADC with Alternative FIR Architecture

ABSTRACTThis paper presents a new smart and compact system dedicated to control the output sampling frequency of an analogue-to-digital converters (ADC) based on single-bit sigma-delta (ΣΔ) modulator. This system dramatically improves the spectral analysis capabilities of power network analysers (power meters) by adjusting the ADC’s sampling frequency to the input signal’s fundamental frequency with a few parts per million accuracy. The trade-off between straightforwardness and performance that motivated the choice of the ADC’s architecture are preliminary discussed. It particularly comes along with design considerations of an ultra-steep direct-form FIR that is optimised in terms of size and operating speed. Thanks to compact standard VHDL language description, the architecture of the proposed system is particularly suitable for application-specific integrated circuit (ASIC) implementation-oriented low-power and low-cost power meter applications. Field programmable gate array (FPGA) prototyping and experimental results validate the adjustable sampling frequency concept. They also show that the system can perform better in terms of implementation and power capabilities compared to dedicated IP resources.

Embedded Platform for Generic High-order Sigma-delta Accelerometers Testing

The transition from an open loop to a closed loop sensing approach in MEMS accelerometers is an important step towards improving the sensor noise performance, bandwidth and time responses [1]. However, this approach presents some computational challenges due to the fast nature of the mechanical part, and ultimately, the performance of the feedback circuit will establish the sensor performance limits that can be accomplished.This paper presents a processor-centric digital platform assisted by an FPGA for real-time control of MEMS accelerometers through a configurable multi-order ΣΔ modulation technology module. The system is designed to allow a high-level fine tune of the system control parameters, such as sensor offset, actuation voltage, sampling frequency, filters coefficients, ΣΔ order and coefficients as well as the output decimation ratio. The processor is used to control the hardware, perform time-critical synchronous operations and provide an external control port through a UART API protocol. The platform has been successfully tested in multiple ΣΔ configurations.

Improved unity‐STF sturdy MASH ΣΔ modulator for low‐power wideband applications

A novel sturdy multi-stage noise-shaping sigma–delta modulator that cancels the first-stage quantisation error at the output of the modulator is presented. Since any stage of the modulator has unity signal transfer function, the modulator would be very robust to circuit non-idealities such as finite op-amp gain. Furthermore, the signal processing timing issue in the critical paths of the proposed topology has been relaxed due to shifting the delay of the last integrator to the feedback path of the modulator. Moreover, this topology can be implemented in the circuit level by a fewer active blocks. Therefore, it practically would be suitable for low-voltage and low-oversampling applications. Simulation results show the usefulness of the proposed modulator.