ΣΔ Modulator Research Articles

A SAR-based ΣΔ modulator using shared DAC

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the ΣΔ modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time ΣΔ modulator is designed and simulated in 0.18 μm CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth.

Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation

Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation

Compensation of Nonlinearities in ΣΔ Modulators Using Digital Assisted Analog Electronics Approach

Compensation of Nonlinearities in ΣΔ Modulators Using Digital Assisted Analog Electronics Approach

MASH ΣΔ modulator with highly reduced in‐band quantisation noise

A novel class of multi-stage noise-shaping ΣΔ modulators is presented. The proposed structure achieves a one-order higher noise-shaping than the modulator's order only by using two extra analogue paths. The noise transfer function zero optimisation is achieved by adjusting a single coefficient in the proposed modulator. Hence, with a minimal extra circuit, the signal-to-noise and distortion ratio is significantly increased compared with the conventional cascaded modulator. Analytical calculations and simulation results are provided to verify the usefulness of the proposed modulator.

Low-distortion bandpass ΣΔ modulator using two-path double-sampling technique

Low-distortion bandpass ΣΔ modulator using two-path double-sampling technique

Indirect-Feedback Sigma-Delta Image Sensors: Theory, Modeling and Design

A novel architecture for a CMOS image sensor that incorporates a column-level sigma-delta (ΣΔ) analog-to-digital converter is presented. An indirect-feedback readout architecture where the digital output of the ΣΔ modulator is accumulated by a digital counter and converted to an analog voltage that serves as the reference voltage in the modulator's comparator is employed. A time-domain pixel simulator that enables assessment of the major noise contributions in this type of imager is also presented. Theoretical calculations agree with simulation results, showing a minimum readout noise of 2.18e- and a dynamic range (DR) of over 100 dB. Prototype chip tests without multiple resets show an 87 dB dynamic range with a readout noise of 2.17e-.

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

A power-efficient improved recycling folded cascode amplifier

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65 nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits.

A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

This paper proposes a new low-power MOS parametric integrator (MPI) for the design of wideband discrete time sigma-delta (ΣΔ) modulators. The MPI is implemented with MOS capacitors, which provide the required gain by switching from inversion in the sampling phase into depletion in the amplification phase. Analysis along with simulation results illustrate that MPI consumes very low power dissipation compared to the conventional active integrators with some negligible performance changes. To verify this, the MPI is used in two wideband ΣΔ modulators, one with 8-bit resolution and the other with 13-bit resolution with input bandwidth and sampling frequency of 12.5 and 200 MHz, respectively. The first one is a second order single stage ΣΔ modulator and the second one is a MASH 2-2 modulator, both implemented in 0.18-μm CMOS technology. Simulation results indicate that these modulators save a significant amount of power consumption when their second integrator is replaced by MPI.

Efficient hybrid continuous-time/discrete-time cascade [formula omitted] modulators for wideband applications

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approach.

Frequency-Agile Multiband Quadrature Sigma-Delta Modulator for Cognitive Radio: Analysis, Design and Digital Post-Processing

A quadrature ΣΔ analog-to-digital converter (ADC) is a promising solution for intermediate frequency digitizing software defined cognitive radio (CR) receivers because of, e.g., multiband capability and power efficiency. However, inherent coefficient mismatches between the in-phase and quadrature rails can severely damage the performance of such receiver by creating mirror-frequency interference (MFI). In this article, a novel frequency-agile and reconfigurable transfer function design, allowing digital post-compensation of the MFI, is proposed. The design is based on a novel closed-form transfer function model for higher-order quadrature ΣΔ modulators (QΣΔMs) under implementation inaccuracies, proposed herein. By doing the compensation in digital domain, it is possible to take into account all error-sources of the receiver chain at once, including, e.g., a quadrature mixer before the ADC. This capability is obtained by preserving the mirror-band signal information and using the noise transfer function of a QΣΔM to remove quantization noise from therein. This is demonstrated in a multiband scenario aimed for CR receivers, where a number of frequency channels can be received and detected in parallel. Practical examples of the transfer function analysis under implementation inaccuracies and the post-compensation performance are given with a two-stage QΣΔM, having stage-orders of four, allowing eighth-order noise shaping.

A 0.8-V 230-$\mu$W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications

This paper presents a ΣΔ modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230-μW power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.

A Low-Distortion Fourth-Order Bandpass Sigma-Delta Modulator Using Double-Sampling Technique

In this paper, a low-distortion fourth-order bandpass sigma-delta (ΣΔ) modulator is proposed based on a switched-capacitor resonator which employs double-sampling technique to relax the requirements for circuits and reduce opamp power consumption and chip area. The modulator is based on the low-distortion low pass ΣΔ modulator. The system level simulation results compare between the low-distortion architecture and the traditional one is given. The full differential circuit applying two-path technique is implemented with TSMC0.18µm CMOS process. It achieves a peak SNR (signal-to-noise ratio) of 85.9dB and DR (dynamic range) of 91dB with 200 kHz bandwidth centered at 20MHz which are better than the conventional bandpass ΣΔ modulator.

Nonlinearity Analysis of Closed-Loop ΣΔ Micro-Mechanical Accelerometer

A high-order interface circuit based on sigma-delta (ΣΔ) modulation is advantageous to enhance the resolution and reduce the quantization noise of micro-accelerometer, while the performance is restricted by the effect of nonlinearity of op-amp, electrostatic force feedback and quantizer. A fifth-order closed-loop ΣΔ capacitive accelerometer is proposed in this paper and a theoretic nonlinearity of the accelerometer was investigated. The nonlinear behavioral models based on SIMULINK are given in the paper. The simulation and test result are presented through optimization based on the nonlinearity analysis at last.

Design of an ultra low power third order continuous time current mode ΣΔ modulator for WLAN applications

This paper presents a third order continuous time current mode ΣΔ modulator for WLAN 802.11b standard applications. The proposed circuit utilized feedback architecture with scaled and optimized DAC coefficients. At circuit level, we propose a modified cascade current mirror integrator with reduced input impedance which results in more bandwidth and linearity and hence improves the dynamic range. Also, a very fast and precise novel dynamic latch based current comparator is introduced with low power consumption. This ultra fast comparator facilitates increasing the sampling rate toward GHz frequencies. The modulator exhibits dynamic range of more than 60dB for 20MHz signal bandwidth and OSR of 10 while consuming only 914μW from 1.8V power supply. The FoM of the modulator is calculated from two different methods, and excellent performance is achieved for proposed modulator.

A Study on Multi-Level PWM and Asynchronous /spl Sigma/ /spl Delta/ Modulations for Enhanced Bandlimited Signal Tracking in Switching Power Amplifiers

This work deals with multi-level switching amplifiers, in the context of high-efficiency power amplification for signal tracking applications. In particular, this paper evaluates the reduction in the error signal's power due to multi-level power amplification (compared to conventional two-level amplifiers) and compares the performance of two multi-level pulse modulations: PWM and Asynchronous ΣΔ Modulation. First the intrinsic bandwidth limits of multi-level switching amplifiers are inferred, to clearly state the advantages and limitations of multi-level power amplification. From the existing analyses of Pulse Width Modulation already reported in the literature, PWM is herein extended to multiple levels based on an equivalent representation, which allows to derive a closed expression for the power spectrum of multi-level PWM in bandlimited signal tracking. The Asynchronous ΣΔ Modulation is extended to multiple levels and the resulting multi-level encoding algorithm is analyzed in both time and frequency domains. The performance of both modulations is characterized and compared at different operating frequencies and using different number of levels. The main outcomes of this in-depth characterization show that, if the switching frequency is high enough, the tracking error is independent of the modulation and the switching frequency, i.e., it only depends upon the number of levels, which points out the suitability of asynchronous modulations for relatively low switching frequencies (compared to the number of levels).

System Design of a Fifth-Order Close-Loop ΣΔ Accelerometer

This paper presents the system design of a high order single loop electromechanical ΣΔ accelerometer. The noise-coupled is employed in the fourth-order feed-forward micro-accelerometer ΣΔ modulator to provide fifth-order noise shaping performance. It is implemented without degrading the loop stability and without changing original loop coefficients of the fourth-order accelerometer.

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

The design and optimization methodology for CT ΣΔ modulators with hybrid Active---Passive (AP) loop-filters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the hybrid AP loop filtering can achieve an approximated noise-shaping function as a fully active ΔΣ modulator with the same order. The ELD effect in the hybrid AP CT ΔΣ modulator which influences the poles and zeros locations of the Noise Transfer Function (NTF) in the modulator is depicted. This paper also investigates the feasibility of applying the ELD compensation techniques that were used to be implemented in the active integrator's case to the hybrid AP CT ΔΣ modulator; however, some of them cannot be practically applied since the passive loop-filter cannot perform proportional feedback signal summation. After the discussion and analysis, the technique similar to Vadipour et al. (In: Symposium on VLSI circuits digest of technical papers, 2008) can be easily implemented at circuit-level and after applying it, there is one additional zero to compensate the peak in the NTF. With the help of this technique, the maximum quantizer delay tolerance can be a full clock period. The mentioned ELD compensation technique was applied in a 2nd order CT ΔΣ modulator with an active-RC integrator as the 1st stage and a passive RC filter as the 2nd stage, which was verified by transistor-level simulations in 65 nm CMOS. The circuit exhibits either 67.3 dB or 65.3 of SNDR, under the effect of half clock period or one clock period ELD, respectively; by contrast, without compensation, the system is unstable with both half or one clock period ELD effect. The designed hybrid CT ΔΣ modulator achieves 2 MHz signal bandwidth and consumes 2.54 mW of power.

A 256 pixel magnetoresistive biosensor microarray in 0.18μm CMOS.

Magnetic nanotechnologies have shown significant potential in several areas of nanomedicine such as imaging, therapeutics, and early disease detection. Giant magnetoresistive spin-valve (GMR SV) sensors coupled with magnetic nanotags (MNTs) possess great promise as ultra-sensitive biosensors for diagnostics. We report an integrated sensor interface for an array of 256 GMR SV biosensors designed in 0.18 μm CMOS. Arranged like an imager, each of the 16 column level readout channels contains an analog front- end and a compact ΣΔ modulator (0.054 mm2) with 84 dB of dynamic range and an input referred noise of 49 nT/√Hz. Performance is demonstrated through detection of an ovarian cancer biomarker, secretory leukocyte peptidase inhibitor (SLPI), spiked at concentrations as low as 10 fM. This system is designed as a replacement for optical protein microarrays while also providing real-time kinetics monitoring.

Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron

A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra power consumption. To cover wide current range due to variable coefficients in different modes, the programmable SI-DAC architecture with 2-bit digital controlled unit cells is proposed. Implemented in 65 nm CMOS, the simulated results verify that the proposed scheme solves the gate-leakage issue and the modulator achieves tremendously high performance of 84.5 dB SQNDR and 94.6 dB SFDR with almost 14 and 19 dB improvement in SQNDR and SFDR, respectively.