Study of closed-loop high-resolution sigma-delta for a MEMS accelerometer

Abstract

In this paper, a high-resolution Sigma-Delta (ΣΔ) modulator in a standard 0.5 µm CMOS technology for a MEMS accelerometer is presented. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a back-end forth-order Sigma-Delta modulator. The low-noise front-end detection circuit is proposed with correlated double sampling (CDS) technique to eliminate the 1/f noise and offset of operational amplifier. The capacitance compensation array is used for rejecting the sensor element mechanical offset. The lead compensator circuit is to ensure the stability of the high-order closed-loop system. The interface is fabricated in a standard 0.5 µm CMOS process and the active circuit area is about 8 mm2. The MEMS accelerometer system consumes 25 mW from a single 7 V supply at a sampling frequency of 250 kHz. The ΣΔ modulator can achieve an effective number of bits 20.30 bits and an average noise floor in low-frequency range of 140 dB.