Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope

Abstract

Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.