Abstract
Micro-electromechanical system (MEMS) accelerometers are widely used in the inertial navigation and nanosatellites field. A high-performance digital interface circuit for a high-Q MEMS micro-accelerometer is presented in this work. The mechanical noise of the MEMS accelerometer is decreased by the application of a vacuum-packaged sensitive element. The quantization noise in the baseband of the interface circuit is greatly suppressed by a 4th-order loop shaping. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a 4th-order Sigma-Delta (ΣΔ) modulator. The stability of high-order ΣΔ was studied by the root locus method. The gain of the integrators was reduced by using the proportional scaling technique. The low-noise front-end detection circuit was proposed with the correlated double sampling (CDS) technique to eliminate the 1/f noise and offset. The digital interface circuit was implemented by 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. The high-performance digital accelerometer system was implemented by double chip integration and the active interface circuit area was about 3.3 mm × 3.5 mm. The high-Q MEMS accelerometer system consumed 10 mW from a single 5 V supply at a sampling frequency of 250 kHz. The micro-accelerometer system could achieve a third harmonic distortion of −98 dB and an average noise floor in low-frequency range of less than −140 dBV; a resolution of 0.48 μg/Hz1/2 (@300 Hz); a bias stability of 18 μg by the Allen variance program in MATLAB.
Highlights
Capacitive accelerometers are widely used in the military and civilian fields because of their low power consumption, simple structure, good stability and easy integration with the complementary metal-oxide-semiconductor (CMOS) process [1]
The noise theory, system stability analysis and key technology of high-precision closed-loop micro-accelerometers are mainly studied in this paper, which is aimed at realizing a high-performance interface circuit chip with sub-μg accuracy
The interface circuit based on micro-accelerometers was fabricated by a 0.35 μm CMOS process and cooperated with Shanghai Huahong Integrated Circuit (Shanghai, China)
Summary
Capacitive accelerometers are widely used in the military and civilian fields because of their low power consumption, simple structure, good stability and easy integration with the complementary metal-oxide-semiconductor (CMOS) process [1]. High over sampling rate (OSR), high-order topology and multi-bit quantization are used to improve the noise shaping ability of Sigma-Delta (Σ∆) micro-accelerometers. The noise theory, system stability analysis and key technology of high-precision closed-loop micro-accelerometers are mainly studied in this paper, which is aimed at realizing a high-performance interface circuit chip with sub-μg accuracy.
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