Schottky-barrier Transistors Research Articles

Noise and sensitivity analysis of the dielectric modulated reconfigurable SiNW-SBT for biosensor applications

For the first time, we reported the noise and sensitivity analysis of the Dielectric Modulated Reconfigurable Silicon Nanowire-based Schottky Barrier Transistor (DMR SiNW-SBT) for biosensor applications. To validate the simulation, we present experimental calibration of the DMR SiNW-SBT biosensor. The biomolecules having different dielectric constants and charge densities are immobilized in the cavity region under the control gate. These biomolecules modulate the Schottky junction width at the source channel interface and enhance the drain current of the biosensor. The simulation results indicate that the proposed device ION and VTH sensitivity improved by 54.65 % and 85.71 %, respectively, with the state-of-the-art biosensors. Noise analysis shows that the NFmin decreased by 190.32 % and offers a low source impedance of 70Ω, which minimizes signal loss and distortion. Additionally, we investigate the linearity parameters that outperformed the FET-based biosensors. The gm3 experiences a reduction of 123.21 %, while the VIP3 sees an increase of 7.87 % and the IIP3 shows a rise of 7.21 %. Furthermore, we have conducted device optimization by varying the cavity length and thickness. We also outline potential fabrication steps for the DMR SiNW-SBT biosensor. Thus, results show that the proposed biosensor emerges as a promising candidate for advanced biosensing applications with high sensitivity, enhanced linearity, and robust noise resilience.

Physics-based compact current model for schottky barrier transistors at deep cryogenic temperatures including band tail effects and quantum oscillations

This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device’s Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc.). For model verification, it is compared to measurements performed on nanowire Schottky barrier transistors at a temperature of 5.5K.

Content-Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing.

As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.

Liquid-Film Rupture for Web-like Ag Nanowires toward High-Performance Organic Schottky Barrier Transistors.

Organic vertical transistors are promising device with benefits such as high operation speed, high saturation current density, and low-voltage operation owing to their short channel length. However, a short channel length leads to a high off-current, which is undesirable because it affects the on-off ratio and power consumption. This study presents a breakthrough in the development of high-performance organic Schottky barrier transistors (OSBTs) with a low off-current by utilizing a near-ideal source electrode with a web-like Ag nanowire (AgNW) morphology. This is achieved by employing a humidity- and surface-tension-mediated liquid-film rupture technique, which facilitates the formation of well-connected AgNW networks with large pores between them. Therefore, the gate electric field is effectively transmitted to the semiconductor layer. Also, the minimized surface area of the AgNWs causes complete suppression of the off-current and induces ideal saturation of the OSBT output characteristics. p- and n-type OSBTs exhibit off-currents in the picoampere range with on/off ratios exceeding 106 and 105, respectively. Furthermore, complementary inverters are prepared using an aryl azide cross-linker for patterning, with a gain of >16. This study represents a significant milestone in the development of high-performance organic vertical transistors and verifies their applicability in organic electronic circuitry.

Vertical Nonvolatile Schottky‐Barrier‐Field‐Effect Transistor with Self‐Gating Semimetal Contact (Adv. Funct. Mater. 19/2023)

Schottky Barriers In article number 2213254, Jian-Bin Xu, and co-workers demonstrate that the vertically stacked Schottky barrier transistor with the semimetal contact enables the simultaneous integration of the electrode and the self-gating function to achieve the reversible direction of photo-generated-charge separation, which envisaged to integrate the nonvolatility and the reconfigurable photo response and build a promising photo-powered reconfigurable in-memory architecture to mimic the brain.

Graphene barristors for de novo optoelectronics.

Graphene-based vertical Schottky-barrier transistors (SBTs), renowned as graphene barristors, have emerged as a feasible candidate to fundamentally expand the horizon of conventional transistor technology. The remote tunability of graphene's electronic properties could endorse multi-stimuli responsive functionalities for a broad range of electronic and optoelectronic applications of transistors, with the capability of incorporating nanochannel architecture with dramatically reduced footprints from the vertical integrations. In this Feature Article, we provide a comprehensive overview of the progress made in the field of SBTs over the last 10 years, starting from the operating principles, materials evolution, and processing developments. Depending on the types of stimuli such as electrical, optical, and mechanical stresses, various fields of applications from conventional digital logic circuits to sensory technologies are highlighted. Finally, more advanced applications toward beyond-Moore electronics are discussed, featuring recent advancements in neuromorphic devices based on SBTs.

Guiding charge injection in Schottky-barrier transistors through the spatial Fermi-level gradients of heterogeneous bimetallic systems

A heterogeneous bimetallic system, composed of two metallic thin films with inherently different Fermi levels, is potentially usable for the fine tuning of interfacial charge dynamics.

Composition Dependent Electrical Transport in Si1-x Gex Nanosheets with Monolithic Single-Elementary Al Contacts.

Si1-x Gex is a key material in modern complementary metal-oxide-semiconductor and bipolar devices. However, despite considerable efforts in metal-silicide and -germanide compound material systems, reliability concerns have so far hindered the implementation of metal-Si1-x Gex junctions that are vital for diverse emerging "More than Moore" and quantum computing paradigms. In this respect, the systematic structural and electronic properties of Al-Si1-x Gex heterostructures, obtained from a thermally induced exchange between ultra-thin Si1-x Gex nanosheets and Al layers are reported. Remarkably, no intermetallic phases are found after the exchange process. Instead, abrupt, flat, and void-free junctions of high structural quality can be obtained. Interestingly, ultra-thin interfacial Si layers are formed between the metal and Si1-x Gex segments, explaining the morphologic stability. Integrated into omega-gated Schottky barrier transistors with the channel length being defined by the selective transformation of Si1-x Gex into single-elementary Al leads, a detailed analysis of the transport is conducted. In this respect, a report on a highly versatile platform with Si1-x Gex composition-dependent properties ranging from highly transparent contacts to distinct Schottky barriers is provided. Most notably, the presented abrupt, robust, and reliable metal-Si1-x Gex junctions can open up new device implementations for different types of emerging nanoelectronic, optoelectronic, and quantumdevices.

Sub-Linear Current Voltage Characteristics of Schottky-Barrier Field-Effect Transistors

This article studies the sub-linearity of the output characteristics measured in Schottky-barrier metal-oxide-semiconductor field-effect transistors with simulations and experiments. It is shown that the sub-linearity is not due to the forward-biased Schottky diode at the drain contact interface but due to the drain bias impact on the source-side Schottky-barrier, resulting in an increased carrier injection with increasing drain–source voltage. The simulation results are confirmed with the measurements of fabricated dual-gate Schottky-barrier transistors.

A Compact Physical Drain Current Model of Multitube Carbon Nanotube Field Effect Transistor Including Diameter Dispersion Effects

Carbon nanotube field-effect transistor (CNTFET) shows great potential for digital and analog applications due to the unique 1-D ballistic carrier transport in carbon nanotubes (CNTs). A new compact physical model for CNT Schottky-barrier transistors is proposed in this article. The Schottky barrier between the contact metal and CNTs is described by using an effective barrier height, and more importantly, the influence of using CNT arrays or networks rather than a single CNT as the device channel is considered in this model. Moreover, the trapping effect is investigated and modeled by adding <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> delay element to the equivalent circuit. The model is proposed in a concise form to avoid complex operations such as integration and is compatible with circuit simulation. The simulation results of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}-{V}$ </tex-math></inline-formula> characteristics are verified to be in agreement with experimental data.

Oxide electronics: Translating materials science from lab-to-fab

Advances in the science and technology of thin-film materials have fueled a myriad of developments in large area electronics. This is particularly true for amorphous oxide semiconductors. Oxides have underpinned a number of technologically significant innovations in displays, sensors, and photovoltaics. Now they are setting the stage for exciting new applications related to flexible electronics and three-dimensional (3D) integration for post-complementary metal oxide semiconductor (CMOS) back-end-of-line processing in the quest for more-than-Moore solutions. This article reviews the development of oxide semiconductors and associated integration processes that have translated materials science fiction to commercial reality on a large scale. These advances have been driven by a host of advantages such as low cost, prudent manufacturing and large area scalability. What makes oxide semiconductors so attractive? These materials have a wide bandgap, which provides for high transparency; a cool feature for seamless embedding of electronics, particularly displays and imagers, for the immersive ambient. The OFF-current in oxide thin-film transistors is ultralow, thanks to the very low density of states in the bandgap. Indeed, this attribute is indispensable to minimize charge leakage in switching transistors and for low power, low-voltage, high-resolution sensor interfaces. More importantly, oxide thin-film transistors can be processed at relatively low temperatures thus making them amenable for 3D integration on post-processed CMOS silicon. This article provides the current status of the oxide semiconductor technology. We review the evolution of oxides based on their functional properties, along with deposition and solution processing techniques for heterostructure thin-film transistors, phototransistors, nanowire image sensors, ultralow power Schottky-barrier transistors, and 3D integration for back-end-of-line CMOS. These devices constitute fundamental building blocks for a new generation of applications ranging from interactive displays and imaging to future 3D electronic systems that are not constrained by form factor.Graphical abstract

Nonvolatile Reconfigurable 2D Schottky Barrier Transistors.

Nonvolatile reconfigurable transistors can be used to implement highly flexible and compact logic circuits with low power consumption in maintaining the configuration. In this paper, we build nonvolatile reconfigurable transistors based on 2D CuInP2S6/MoTe2 heterostructures. The ferroelectric polarization-induced electron and hole doping in the heterostructure are investigated. By introducing the ferroelectric doping into the source/drain contacts, we demonstrate reconfigurable Schottky barrier transistors, whose polarity (n-type or p-type) can be dynamically programmed, where the configuration is nonvolatile in nature. These transistors exhibit a tunable photoresponse, where the n-n doping state leads to negative photocurrent, whereas the p-p doping state gives rise to a positive photocurrent. The transistor with asymmetric (n-p or p-n) contacts exhibits a strong photovoltaic effect. These reconfigurable logic and optoelectronic transistors will enable a new type of device fabric for future computing systems and sensing networks.

Hot-carrier-induced device degradation in Schottky barrier ambipolar polysilicon transistor

This study experimentally investigated the hot-carrier-induced device degradations in Schottky barrier (SB) ambipolar polysilicon transistors and validated the degradation mechanism. The behavior of hot-carrier-induced device degradation in SB ambipolar transistors was different from that of a unipolar MOSFET. The phenomenon of hot-carrier generation at the source electrode, attributed to the existence of a high electric field across the reverse-biased source electrode in SB transistors and the competing degradation mechanism between the trapped charges at the gate oxide near the source edge and drain electrode, explained the experimental results. The degradation mechanism was justified by measuring the gate current and transfer characteristics in the forward and reverse modes before and after hot-carrier stress, respectively. The results can contribute to the non-volatile memory applications and aid in investigating the aging effects of multi-functional integrated circuits using reconfigurable field-effect transistors.

Mobility Extraction in 2D Transition Metal Dichalcogenide Devices-Avoiding Contact Resistance Implicated Overestimation.

Schottky barrier (SB) transistors operate distinctly different from conventional metal-oxide semiconductor field-effect transistors, in a unique way that the gate impacts the carrier injection from the metal source/drain contacts into the channel region. While it has been long recognized that this can have severe implications for device characteristics in the subthreshold region, impacts of contact gating of SB in the on-state of the devices, which affects evaluation of intrinsic channel properties, have been yet comprehensively studied. Due to the fact that contact resistance (RC ) is always gate-dependent in a typical back-gated device structure, the traditional approach of deriving field-effect mobility from the maximum transconductance (gm ) is in principle not correct and can even overestimate the mobility. In addition, an exhibition of two different threshold voltages for the channel and the contact region leads to another layer of complexity in determining the true carrier concentration calculated from Q = COX * (VG -VTH ). Through a detailed experimental analysis, the effect of different effective oxide thicknesses, distinct SB heights, and doping-induced reductions in the SB width are carefully evaluated to gain a better understanding of their impact on important device metrics.

Temperature-dependent performance of Schottky-Barrier FET ultra-low-power diode

In this paper, for the first time, we apply the ultra-low-power (ULP) diode concept with Schottky Barrier (SB) transistors and analyze their performance in comparison to standard CMOS, using calibrated TCAD mixed-mode simulations. The negative impedance characteristics obtained in reverse mode with SB devices are shown to offer more stable current characteristics compared to CMOS, especially as a function of temperature. The origin of this behavior manifests itself in the fact that carriers tunneling through the barrier by field emission and carriers overcoming the barrier by thermionic emission both contribute to the total device current. This enables superior current performance over temperature. This enables ultra-low-power memory application over a larger temperature range, or with a denser cell area.

Tunable Schottky contact in graphene/InP3 van der Waals heterostructures

To date, the study of contact behavior between graphene and two-dimensional semiconductors is an open topic. Here, we carry out the density-functional-theory to calculate graphene/InP3 van der Waals heterostructures. The results share that low binding energy and mechanical stability ensure that graphene/InP3 heterostructures can be prepared in the experiment. Moreover, n-type Schottky barrier is found in graphene/InP3 heterostructures. Shortening the layer spacing induces a shift of Schottky contact from n- to p-type, and finally makes graphene/InP3 heterostructures to be semiconductors under a large compressive strain. In addition, we design the Schottky barrier transistor on the basis of modulated contact type (Schottky to Ohmic contact) under external electric field, which also can tune the doping of graphene in graphene/InP3 heterostructures. These findings are of utmost significance to guiding the design of new generation graphene-based contact.

Schottky-Junction TMD-Based Monomaterial Field-Effect Transistor

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have attracted extensive interest as this class of layered materials exhibit electronic properties from semimetals to semiconductors. In addition, their properties may significantly change when moving from bulk to ultra-thin films due to strong spin-orbit coupling (SOC) [1-3]. These properties open up new opportunities in bandgap engineering for future electronic and photonic devices.Our recent study of platinum diselenide (PtSe2) films demonstrates that PtSe2 has distinct thickness-dependent electronic structures and physical properties [4]. Although the bulk crystal is a semimetal with an indirect overlap of the conduction and valence bands, monolayer PtSe2 has been revealed to be a semiconductor [4-6]. The possibility of making semimetal hetero-dimensional junctions with uniform chemical bonding at the interface promises the possibility of fabricating ideal Schottky barriers closely mirroring the behaviour of an ideal junction [7,8]. As a result, it is proposed to consider ‘thick’ (semimetallic) PtSe2 as the source and drain contact regions and ‘thin’ (semiconducting) PtSe2 region as the channel (gated) region. The electronic structure of the PtSe2-based Schottky barrier transistor is determined based on density functional theory (DFT). The DFT Hamiltonian is used to determine electrode self-energies to describe ‘semi-infinite’ electrodes achieved by periodic extension of the 3D semimetallic and the 2D semiconducting regions at distances away from the junctions, implemented in the Atomistix ToolKit (ATK) [9,10]. An explicit device region encompassing the junction regions is then treated by adding the energy-dependent complex self-energies to the device region Hamiltonian. Including the self-energies explicitly opens the system by application of the boundary conditions suitable for non-equilibrium Green's function (NEGF) using the self-energies calculated for semi-infinite electrodes. In directions parallel to the interface, periodic boundary conditions are applied leading to a 3D region in direct contact to a 2D thin film (see Fig. 1(a)).This structure is expected to improve the contact resistance. This structure could also be beneficial for the performance of short-channel devices due to the resonance states originated at the thick-thin interface [8]. Based on the semimetal-to-semiconductor transition, where the value of the induced gap is controlled by varying the film thickness, a Schottky barrier transistor is designed. Ab-initio calculations combined with the NEGF formalism for charge transport determine the device current-voltage characteristics. Output characteristic of a back-gated structure (inset of Fig. 1(b)) shows that the proposed device is OFF at VGS = -0.5 V while at VGS = 1.5 V it is at ON state with ION/IOFF > 108. This current modulation confirms the potential application of such monomaterial field effect transistor with no doping for low-power electronics. In this study, we are also investigating the energy resolved local density of states (LDoS) and charge transfer at the semimetal-gated region interface which provides insight into the physics of the performance of the devices.Another advantage of the proposed FET structure is that it does not require any doping at any of the thick (metallic) or thin (channel) regions, which makes the fabrication considerably more feasible. However, vacancies have shown to influence the band structure [4]; hence, such point defects are considered in the structure, and their impact on the device performance will be presented.

Percolation-Limited Dual Charge Transport in Vertical p-n Heterojunction Schottky Barrier Transistors.

Solution-processed, high-speed, and polarity-selective organic vertical Schottky barrier (SB) transistors and logic gates are presented. The organic layer, which is a bulk heterojunction (BHJ) composed of PBDB-T and PC71BM, is employed to simultaneously realize vertical electron and hole transports through the separate p-channel and n-channel. The gate-modulated graphene work functions enable broad modulation of SB heights at both the graphene-PBDB-T and graphene-PC71BM heterointerfaces. Interestingly, the fine-tuned energy-level alignment enables an exclusive injection of holes or electrons unlike conventional BHJ-based ambipolar transistors, leading to a clear transition between p-channel and n-channel single-carrier-like transistor characteristics. Furthermore, the improved percolation-limited dual charge transport in vertical architecture results in high charge carrier density and high-speed on-off switching characteristics, providing a high on-off current ratio exceeding 105 and an operation speed of 100 kHz. Solution-based on-substrate fabrications of low-power complementary logic gates such as NOT, NOR, and NAND are also successfully performed.

All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics.

In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium-tin-oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm-2, a high on-off current ratio of 106, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.

Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration.

This paper introduces a strategy to modulate a Schottky barrier formed at a graphene-semiconductor heterojunction. The modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene-semiconductor junction, which we refer to as the remote gating of a Schottky barrier. The remote gating relies on the sensitive work function of graphene, whose local variation induced by locally applied field effect affects the change in the work function of the entire material. Using Kelvin probe force microscopy analysis, we directly visualize how this local variation in the work function propagates through graphene. These properties of graphene are exploited to assemble remote-gated vertical Schottky barrier transistors (v-SBTs) in an unconventional device architecture. Furthermore, a vertical complementary circuit is fabricated by simply stacking two remote-gated v-SBTs (pentacene layer as the p-channel and indium gallium zinc oxide layer as the n-channel) vertically. We consider that the remote gating of graphene and the associated device architecture presented herein facilitate the extendibility of graphene-based v-SBTs in the vertical assembly of logic circuits.