Schottky-barrier Field-effect Transistors Research Articles

Preferential diffusion and orientation effects of Schottky barrier GaAs field-effect transistors

Preferential diffusion and the corresonding orientation effect was examined for GaAs Schottky barrier field-effect transistors. Unreported orientation effects of devices with no n+ implants are presented and compared to self-aligned n+-implanted devices. Characteristics of the intrinsic and extrinsic field-effect transistors were measured for devices oriented in the [011] and [011̄] directions. Enhanced diffusion due to anisotropic stress is proposed as the mechanism. Criteria for preferred device orientation and ambiguities in previous literature are discussed.

Orientation effect reduction through capless annealing of self-aligned planar GaAs Schottky barrier field-effect transistors

A reduction in the orientation effect on self-aligned ion-implanted planar GaAs Schottky barrier field-effect transistors (FET’s) has been found. The FET’s were fabricated using capless annealing to avoid thermal stress that occurs at a dielectric/GaAs interface during capped annealing. Both mean and standard deviation in FET threshold voltage as a function of gate length are compared for FET’s oriented in the two perpendicular [110] directions. Very little orientation dependence is observed. Similar high-speed switching operation is also found for either orientation. These results indicate that stress-enhanced preferential lateral diffusion which appears to be a major factor in the orientation effect can be reduced through capless annealing.

GaAs microcircuit contact and interconnect technology

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance. The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature. The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

Orientation effect of self-aligned source/drain planar GaAs Schottky barrier field-effect transistors

The effect of orientation on self-aligned source/drain planar GaAs Schottky barrier field-effect transistors (FET’s) has been investigated. The dependence of the threshold voltage of FET’s on gate length was measured for FET’s oriented in two perpendicular [110] directions. Both stress-enhanced lateral spread of implanted ions and lateral diffusion at the gate material/GaAs interface are proposed as possible mechanism to account for the orientation effect. The experiments indicate that the preferred direction for the self-aligned FET fabrication on a (100) substrate is [011̄].

Influence of AlxGa1−xAs buffer layers on the performance of modulation-doped field-effect transistors

Normally-off and pseudo-normally-on modulation-doped Al0.3Ga0.7As/GaAs Schottky barrier field-effect transistors were fabricated and characterized. The structures were grown by molecular beam epitaxy and exhibited electron mobilities as high as 8000, 100 000, and 200 000 cm2/Vs at 300, 78, and 10 K, respectively. Inclusion of an Al0.3Ga0.7As buffer layer between the substrate and the modulation-doped layers improved the transconductance and saturation characteristics substantially. This improvement was observed to be strongly dependent on the substrate temperature during the buffer layer growth, with the best results being obtained at 700 °C.

An accurate JFET/MESFET model for circuit analysis

An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III– V compounds and with insulating substrates is straightforward. The model is compared to experimental data.

GaAs MESFET's by molecular beam epitaxy

The noise performance of T shaped Ti/W/Au gate GaAs Schottky-barrier field-effect transistors fabricated on channel layers grown by molecular-beam epitaxy (MBE) is reported. The nominal gate length was about 0.7 µm with a total gate width of 250 µm. Typical noise figure and the associated gain were 1.2 and 14 dB at 4 GHz, and 1.9 and 8.5 dB at 12 GHz. To out knowledge these are the best results reported to date on devices fabricated using MBE-grown GaAs. These preliminary results show the promise of MBE for high-quality GaAs FET's.

GaAs Microcircuit Contact and Interconnect Technology

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance.The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature.The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

Short-channel GaAs FET fabricated like a MESFET but operating like a JFET

Normally-on GaAs field-effect transistors (FETs) having 1 ?m gate lengths and 4 ?m channel lengths were fabricated in structures grown by molecular beam epitaxy (MBE). The unique part of this device is the very thin p+/n+ structure used to replace the conventional Schottky barriers. The device fabrication procedure is identical to that of a Schottky barrier FET (MESFET), but the devices exhibit characteristics similar to that of a junction field-effect transistor (JFET). This new device, the `camel diode gate FET?, is expected to have applications in both logic and power devices.

Schottky-barrier field-effect transistor with static-induction principle (MESSIT)

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Electron beam modulation of GaAs metal-semiconductor field-effect transistors

Modulation of the surface potential of GaAs Schottky barrier field-effect transistors by 1–6-kV electrons with current densities in the range between 10−5 and 10−3 A/cm2 can produce current gains G⩾105 for electron beam currents pulsed at rates ⩽104 Hz.

Comparative logic figure of merit of current high-speed transistors

A logic figure of merit is used for the comparative measure of speed of three transistors that represent current technology applied to high-speed transistors. An indium phosphide Schottky-barrier field-effect transistor with a channel length of 1 /spl mu/m has T/SUB FM/=69.2 ps. A gallium arsenide field-effect transistor of essentially the same geometry has T/SUB FM/=80.7 ps. A silicon bipolar transistor with an active base-width of 0.08 /spl mu/m and 5/spl times/0.4 emitter stripes has T/SUB FM/=113.8 ps with package included and T/SUB FM/=65.2 ps for chip only.

Orientation effect on planar GaAs Schottky barrier field effect transistors

Orientation effects on planar GaAs Schottky barrier field effect transistors (MESFET’s) have been found. Device characteristics of FET’s parallel to both [110] directions and both [100] directions are compared. Dependence of the characteristics on gate length has been measured for FET’s oriented in two perpendicular [110] directions. Preferential lateral diffusion is proposed to be the reason underlying these phenomena.

A MESFET model for circuit analysis

A model for silicon Schottky barrier field-effect transistors (Si MESFETs) with micron and submicron dimensions has been implemented in the integrated circuit simulation program SPICE2. A description of the model and its implementation is given, together with a discussion of the physical effects that are important in submicron channel length Si MESFETs. The model is compared with d.c. experimental data with an emphasis on temperature dependence.

Monte carlo particle simulation of n-type GaAs field-effect transistors with a p-type buffer layer

The Monte Carlo particle model of GaAs Schottky-barrier field-effect transistors developed at Reading has been applied to describe a new f.e.t. geometry in order to establish the noise performance. The effect of introducing a p-type layer between the epilayer and the substrate is examined and the d.c. characteristics obtained are presented. By varying the thicknesses of both the epilayer and the buffer layer, as well as the doping of the latter, an optimal design has been arrived at. However, the transconductance of this optimal design is very sensitive to the thickness of the epilayer.

Micrometre-gate m.e.s.f.e.t.s on laser-annealed polysilicon

Schottky-barrier field-effect transistors (m.e.s.f.e.t.s) have been fabricated on uniformly doped laser-annealed polycrystalline silicon deposited on a silicon nitride insulator. The devices, which had aluminium Schottky-barrier gates and diffused n+ sources and drains but nonoptimised channel profiles, had about 65% the gm values of similar but optimised devices made on s.o.s. layers. Performance of these devices is considered adequate for certain innovative integrated-circuit technologies.

A simple model for determining effects of negative differential mobility and magnitude of saturated velocity on the performance of Schottky-barrier field effect transistors

The effects of nonuniform fields in the channel of GaAs MESFETs, and the resulting range of velocities with which carriers drift, are here considered using a simple model in order to determine the effects of negative differential mobility and saturated velocity on the performance of these devices, and of devices made of other materials. On the basis of the equilibrated velocity-field ν( E) characteristic for GaAs, carriers in short-channel FETs drift over much of the source to drain length with the saturated high field velocity, i.e. a velocity about half that used in most previous analytical solutions for GaAs FETs, and one about equal to the maximum carrier velocity in Si. Neglecting transient effects in electron transport, fields at which a negative differential mobility occurs exist over only a very small portion of the channel. The value of low field mobility of the MESFET material is therefore important primarily in determining source resistance.

Hall effect measurements on flash evaporated cadmium sulphide thin films : Z. Szalmassy and L. Wilmes. Vacuum29, (2) 83

An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III–V compounds and with insulating substrates is straightforward. The model is compared to experimental data.

Medium power 12–18 GHz amplifier module

Broadband Ku-band amplification has been extended into the range of medium power levels. A single-ended 100 mW amplifier stage has been developed for the 12--18 GHz frequency band using a GaAs Schottky-barrier field-effect transistor. Minimum gain at 20 dBm of output power was 4dB. When operating in the driver mode, a minimum gain of 5dB at an output power of 15 dBm was measured across Ku-band. Higher gains can easily be achieved by cascading several of these amplifier stages. Gain, output power and impedance characteristics as a function of frequency are discussed.

ChemInform Abstract: GALLIUM ARSENIDE PHOSPHIDE SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR

Chemischer InformationsdienstVolume 8, Issue 24 Physical Inorganic Chemistry ChemInform Abstract: GALLIUM ARSENIDE PHOSPHIDE SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR R. K. PANCHOLY, Search for more papers by this authorW. W. GRANNEMANN, Search for more papers by this author R. K. PANCHOLY, Search for more papers by this authorW. W. GRANNEMANN, Search for more papers by this author First published: June 14, 1977 https://doi.org/10.1002/chin.197724009AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat No abstract is available for this article. Volume8, Issue24June 14, 1977 RelatedInformation