Schottky-barrier Field-effect Transistors Research Articles

Suppression of short channel effects in 5.1 nm WTe2 in-plane Schottky barrier field-effect transistors by Mo-doping

Single layer Schottky barrier field-effect transistors (SBFETs) composed of the in-plane (IP) hetero-junctions of 1T-WTe2(metallic phase WTe2) and 2H–WTe2(semiconducting phase WTe2) have been proposed in this paper. However, the transfer characteristic show that the 5.1 nm IP 1T-2H-1T WTe2 SBFET cannot suppress the short channel effect causing the leakage current beyond the OFF current (IOFF) requirement (0.1 μA/μm) of the International Technology Roadmap for Semiconductors (ITRS, 2013 version) for production in 2028. To solve this problem, we replace the W atoms of 2H–WTe2 near the source electrode with Mo atoms to conquer the short channel effect. We found that the leakage currents of the 5.1 nm IP 1T-2H-1T WTe2 SBFETs decrease gradually with the increase of the number of substitution Mo atoms. When the number of substitutions increases to six periods, the leakage drain current of the 5.1 nm IP 1T-2H-1T WTe2 SBFETs is lower than 0.1 μA/μm. Fortunately, the corresponding ON current (ION) is 961 μA/μm which also conforms to the ON current requirement (900 μA/μm) of ITRS (2013 version) for production in 2028. Therefore, the monolayer WTe2 with the Mo atom substitution also can be used as the channel material in future 5 nm transistor.

Electronic and optical properties and device applications for antimonene/WS2 van der Waals heterostructure

The antimonene and WS2 monolayers have widely studied recently. Here, we construct the Sb/WS2 van der Waals heterostructures to explore their combined effects on electronic and optical properties based on density functional method. The calculated results show that the most stable heterostructure is a type-Ⅱ semiconductor with a medium band gap of 1.183 eV. The external electric field can alter its band gap significantly, for example, the small negative electric field can make the band gap narrowed sharply and linearly. Based on this behavior, a high-performance heterostructure Schottky-barrier field effect transistor is designed. And under vertical strain, the heterostructure is robust to sustain a type-Ⅱ band alignment, but the band gap can be reduced rapidly by pressure. Accordingly, a strain-gated high switch-ratio mechanical switch device by working reversibly between the “compressive” and “unstrained” states is suggested. Also shown is that this heterostructure prefers the visible light adsorption, and the photoelectric power conversion efficiency (PCE) is as high as 20.98%. Particularly, under small positive electric field, the light adsorption and PCE for this heterostructure is enhanced significantly up to 22.845%. Thus a photovoltaic cell with a high PCE is proposed.

The in-plane graphene and boropheneβ12 contacted sub-10 nm monolayer black phosphorous Schottky barrier field-effect transistors

Using ab initio quantum transport calculations, we investigate the performance of the in-plane (IP) graphene and boropheneβ12 contacted sub-10 nm (gate length = 5.1, 6.1, 7.3, 8.8 nm) single-gated (SG) and double-gated (DG) monolayer (ML) black phosphorous (BP) Schottky barrier field-effect transistors (SBFETs). The transfer characteristics, total gate capacitance, intrinsic delay time and dynamic power indicator are studied. The calculated on-state currents of the IP graphene contacted sub-10 nm SG ML BP SBFETs are 1064.8, 1272.3, 1676.5, 1363.8 μA/μm, which are far beyond the requirements of International Technology Roadmap for Semiconductor (ITRS) high performance (HP) application targets. Compared with graphene electrode, the on-state currents of IP boropheneβ12 contacted sub-10 nm SG ML BP SBFETs can only satisfy about 10%–70% requirement of HP standards because of the strong metal induced gap states (MIGS) in the channel. Moreover, we further investigated the effect of DG model on the device performance. The results indicated that the gate electrostatic control is significantly improved by using DG model. The on-state currents of IP graphene and boropheneβ12 contacted sub-10 nm DG ML BP SBFETs are increased by a factor of 1.37–1.56 and 1.16–3.59 compared with SG model. As a result, the large on-state currents of IP configurations based on graphene/ML BP/graphene can greatly stimulate the potential of BP transistors.

Plasmon-assisted polarization-sensitive photodetection with tunable polarity for integrated silicon photonic communication systems

To establish high-bandwidth chip-to-chip interconnects in optoelectronic integrated circuits, requires high-performance photon emitters and signal receiving components. Regarding the photodetector, fast device concepts like Schottky junction devices, large carrier mobility materials and shrinking the channel length will enable higher operation speed. However, integrating photodetectors in highly scaled ICs technologies is challenging due to the efficiency-speed trade-off. Here, we report a scalable and CMOS-compatible approach for an ultra-scaled germanium (Ge) based photodetector with tunable polarity. The photodetector is composed of a Ge Schottky barrier field effect transistor with monolithic aluminum (Al) source/drain contacts, offering plasmon assisted and polarization-resolved photodetection. The ultra-scaled Ge photodetector with a channel length of only 200 nm shows high responsivity of about R = 424 A W−1 and a maximum polarization sensitivity ratio of TM/TE = 11.

The in-plane metal contacted 5.1 nm Janus WSSe Schottky barrier field-effect transistors

Edge contact between two-dimensional materials and metal can achieve small contact resistance because of strong interaction. In this work, we investigated the electronic transport of in-plane (IP) heterojunctions based on Ti/WSSe and Sn/WSSe using first-principle calculations. The results showed the interface bonding and metallization on the IP Ti/WSSe and Sn/WSSe contact interface, indicating the Ohmic contacts between Ti, Sn and WSSe. Then, we constructed a double-gate model to investigate the performance of the IP Ti and Sn contacted 5.1 nm WSSe Schottky barrier field-effect transistors (SBFETs). The calculated on-state current of the IP Ti contacted 5.1 nm WSSe SBFETs is 406.3 μA μm−1. However, the on-state current of the Sn contacted 5.1 nm WSSe SBFETs reaches up to 1104.2 μA μm−1, which is far beyond the requirements of the International Technology Roadmap for Semiconductor HP application targets. Our study will provide a guide for high-performance transistors based on IP metal/WSSe configurations in the future.

Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications.

Artificial synapses based on ferroelectric Schottky barrier field-effect transistors (FE-SBFETs) are experimentally demonstrated. The FE-SBFETs employ single-crystalline NiSi2 contacts with an atomically flat interface to Si and Hf0.5Zr0.5O2 ferroelectric layers on silicon-on-insulator substrates. The ferroelectric polarization switching dynamics gradually modulate the NiSi2/Si Schottky barriers and the potential of the channel, thus programming the device conductance with input voltage pulses. The short-term synaptic plasticity is characterized in terms of excitatory/inhibitory post-synaptic current (EPSC) and paired-pulse facilitation/depression. The EPSC amplitude shows a linear response to the amplitude of the pre-synaptic spike. Very low energy/spike consumption as small as ∼2 fJ is achieved, demonstrating high energy efficiency. Long-term potentiation/depression results show very high endurance and very small cycle-to-cycle variations (∼1%) after 105 pulse measurements. Furthermore, spike-timing-dependent plasticity is also emulated using the gate voltage pulse as the pre-synaptic spike and the drain voltage pulse as the post-synaptic spikes. These findings indicate that FE-SBFET synapses have high potential for future neuromorphic computing applications.

Lateral heterostructures of zigzag phosphorene nanoribbons as a platform for high performance 5 nm transistor

By performing first-principle transport calculations, we propose that lateral heterostructures of zigzag phosphorene nanoribbons (ZPNRs) with the different passivated edges, can represent a powerful platform for the high performance field-effect transistors (FETs). The ZPNR with H-passivated edge is a semiconductor with a band gap of 1.39 eV. However, the ZPNRs with zigzag edges and cliff edges all exhibit the metallic characters. Two 5 nm Schottky barrier FETs consisting of H-passivated ZPNR and unpassivated ZPNRs with zigzag or cliff edges all can overcome the short channel effect. More importantly, the 5 nm Schottky barrier FET consisting of H-passivated ZPNR and unpassivated ZPNRs with cliff edge at a supply voltage of 0.64 V exhibits ION/IOFF ratio larger than 103, which satisfy the requirements of the high-performance transistor outlined by the ITRS (International Technology Roadmap for Semiconductors). Therefore, the transistor model of ZPNRs in this paper provides a valuable idea for the design of short channel transistors in the future.

In-plane Schottky-barrier field-effect transistors with a 4-nm channel based on 1T/2H MoTe2 and WTe2

As state-of-the-art fabrication techniques are approaching the 3 nm size, the traditional silicon-based circuit faces huge challenges. Transistors based on two-dimensional (2D) materials have attracted much attention as potential alternative candidates. However, critical performances including the subthreshold swing (SS), on/off ratio, and magnitude of the on-state current for 2D transistors around 3 nm size are far less to be studied well. In this work, we propose in-plane Schottky-barrier field-effect transistors (SBFETs) with a 4-nm channel based on the lateral heterostructure of monolayer 1T/2H MoTe2 and WTe2. The electric transport properties are investigated by first-principles quantum transport simulations. At a 0.64 V bias, the WTe2 SBFET has an on-state current of 3861 μA/μm, with a 4.5 × 104 on/off ratio and an SS of 87 mV/dec, while the MoTe2 SBFET has an on-state current of 1480 μA/μm, with a large on/off rate of 3.6 × 105 and an SS of 78 mV/dec. Our results suggest that FETs based on the lateral heterostructure of 1T/2H MoTe2 (WTe2) are promising candidates for high-performance 2D transistors.

Simulations of monolayer SiC transistors with metallic 1T-phase MoS2 contact for high performance application* *Project supported by the National Natural Science Foundation of China (Grant Nos. 12074046 and 12074115), the Hunan Provincial Natural Science Foundation of China (Grant Nos. 2020JJ4597, 2021JJ40558, and 2021JJ30733), the Scientific Research Fund of Hunan Provincial Education Department, China (Grant Nos. 20K007 and 20C0039), and the

We preform a first-principles study of performance of 5 nm double-gated (DG) Schottky-barrier field effect transistors (SBFETs) based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS2 contacts. Because of the wide bandgap of SiC, the corresponding DG SBFETs can weaken the short channel effect. The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors. Moreover, the bilayer metallic 1T-phase MoS2 contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees. The above results are helpful and instructive for design of short channel transistors in the future.

Technique for Fabricating Ferromagnetic/Silicon Active Devices and Their Transport Properties

Semiconductor nanowires are unique materials for studying nanoscale phenomena; the possibility of forming silicon nanowires on bulk silicon-on-insulator substrates in a top-down process ensures complete incorporation of this technology into integrated electronic systems. In addition, the use of ferromagnetic contacts in combination with the high quality of ferromagnetic–semiconductor interfaces open up prospects for the use of such structures in spintronics devices, in particular, spin transistors. A simple approach is proposed to create semiconductor nanowire-based active devices, specifically, bottom-gate Schottky-barrier field-effect transistors with a metal (Fe) source and drain synthesized on a silicon-on-insulator substrate and the transport characteristics of the designed transistors are investigated.

Channel Length-Dependent Operation of Ambipolar Schottky-Barrier Transistors on a Single Si Nanowire.

For use in flexible, printable, wearable electronics, Schottky-barrier field-effect transistors (SB-FETs) with various channel materials including low-dimensional nanomaterials have been considered so far due to their comparatively simple and cost-effective integration scheme free of junction and channel dopants. However, the electric conduction mechanism and the scaling properties underlying their performance differ significantly from those of conventional metal-oxide-semiconductor (MOS) field-effect transistors. Indeed, an understanding of channel length scaling and drain bias impact has not been elucidated sufficiently. Here, multiple ambipolar SB-FETs with different channel lengths have been fabricated on a single silicon nanowire ensuring a constant nanowire diameter. Their length scaling behavior is analyzed through drain current and transconductance contour maps, each depending on the drain and gate bias. The reduced gate control and extended drain field effect on Schottky junctions were observed in short channels. Activation energy measurements showed lower sensitive behavior of the Schottky barrier to gate bias in the short-channel device and confirmed the thinning of Schottky barrier width for electrons at the source interface with drain bias.

Impact of Gate–Source/Drain Underlap on the Performance of Monolayer SiC Schottky-Barrier Field-Effect Transistor

Schottky-barrier field-effect transistors (SBFETs) based on 2-D semiconductorshad been investigatedas a substitute for a conventional metal-oxide-semiconductor field-effect transistor (MOSFET) based on bulk silicon in the field of high-performance (HP) device. Especially, the monolayer SiC has been studied because it has a large band gap, which results in reducing the short-channel effect. In this article, the gate-source/drain underlap-dependent characteristics of HP SBFETs based on monolayer SiC with 5.1and 4.6-nm gate lengths are investigated through ab initio simulations. The performances of the 5.1-nm monolayer SiC SBFET are degraded by the gate-source/drain underlap. The gate-source/drain underlap, however, shows the different improved performances for the 4.6-nm monolayer SiC SBFET. The gate-source underlap could enhance the ON-current to 2792 μA/μm and the gate-drain underlap can enhance the ON-current to 1754 μA/μm, which all far exceed the International Technology Roadmap for Semiconductors (ITRS) requirement.

Quantitative, experimentally-validated, model of MoS2 nanoribbon Schottky field-effect transistors from subthreshold to saturation

We investigate the channel length dependence of the electrical characteristics of chemical vapor transport (CVT)-grown MoS2 nanoribbon (NR) Schottky barrier field-effect transistors to provide insights into the transport properties of such nanostructures. The MoS2 NRs form spontaneously during the CVT growth, without the application of etching. Back gated transmission line measurement FETs were fabricated on a 45μm-long NR with channel lengths ranging between 200 nm and 3μm. Contact and sheet resistances were extracted from the electrical measurements and their back-gate bias dependence was analyzed. Numerical modeling based on a virtual probe approach combined with the Landauer formalism shows excellent agreement with the measurements. The model enables a quantitative extraction of the intrinsic FET properties, e.g., mean-free-path and electron mobility, and their dependence on carrier density and investigation of plausible trap distributions. A record electron mobility for a MoS2 NR channel of ∼81cm2/Vs was achieved.

Ohmic contact in graphene/SnSe2 Van Der Waals heterostructures and its device performance from ab initio simulation

Van der Waals (vdW) type metallic/semiconducting heterostructures have attracted much attention for applications like nanoelectronics. The electronic properties of graphene/SnSe2 vdW heterostructure are investigated by the first-principles calculation. The band dispersions of both the graphene and SnSe2 layers are well preserved in the graphene/SnSe2 vdW heterostructure. Notably, n-type Ohmic contact is found at the graphene/SnSe2 vdW interface so that graphene is a fantastic electrode for the SnSe2 Schottky barrier field-effect transistor (SBFET). The on-state current of the 10-nm-gate-long ML SnSe2 SBFET with graphene electrode is 1535 µA/µm for high-performance (HP) application, which is twice that of the ML MoS2 SBFET with bulk Ti electrode and exceeds the requirement of the International Technology Roadmap for Semiconductors for HP devices.

Synthesis and transport properties of FET based on Heusler alloy thin films formed by rapid thermal annealing

In this work we show a preparation technique of Co2FeSi full-Heusler alloy thin films on silicon-on-insulator (SOI) substrates, employing rapid thermal annealing (RTA). The films of the Co2FeSi alloy were formed by a silicidation reaction, caused by RTA, between the ultrathin SOI (001) layer and the Fe/Co layers deposited on it. It is assumed that this technology is compatible with the process of formation of a half-metal source-drain in an advanced CMOS and SOI technology and will be applicable for the manufacture of a source-drain of a field-effect transistor. Schottky barrier field-effect transistors (FET) with a back-gate, based on silicon nanowires with source and drain of a Co2FeSi film, synthesized on an SOI substrate, were manufactured. The transport properties of the device were investigated.

High-Performance Schottky-Barrier Field-Effect Transistors Based on Monolayer SiC Contacting Different Metals

Schottky-barrier field-effect transistors (SBFETs) based on monolayer SiC contacting four metals (Ag, Au, Al, and Pd) have been proposed using density functional theory and ab initio simulations. The n-type Schottky contacts could be formed between monolayer SiC and Ag, Au electrodes with electron Schottky barrier heights (SBHs) of 0.7 and 1.1 eV, respectively, whereas the p-type Schottky contacts were formed between monolayer SiC and Al, Pd electrodes with hole SBHs of 1.0 and 0.1 eV, respectively. When the gate length was equal to 5.1 nm, SiC-SBFETs with four metals could all overcome the short-channel effect due to the wide bandgap of SiC. In addition, the SiC-SBFET with Pd electrode provided the best performance and could satisfy the performance requirement of high-performance transistor with gate length of 5.1 nm outlined by the International Technology Roadmap for Semiconductors (ITRS). Our study gives an insight into the monolayer SiC–metal interfaces and, thus could be developed into a viable 5-nm “More than Moore” device in the future.

Toward CMOS like devices from two-dimensional channel materials

This research update explains in detail the critical aspects of Schottky barrier (SB) field-effect transistors (FETs) for circuit implementations. In particular, it focuses on two-dimensional (2D) channel materials such as black phosphorus. After an initial tutorial about the operation of SB-FETs, this article discusses various scaling approaches and how proper unipolar device characteristics from 2D layered materials can be obtained. Various transistor layouts described in the literature are evaluated in terms of the achieved device performance specs, and the most advanced experimental approach is presented that combines proper scaling, source/drain work function engineering, and gating. This article closes by highlighting the performance of an inverter obtained from properly designed BP-based n-type and p-type transistors.

Dielectrically Modulated Source-Engineered Charge-Plasma-Based Schottky-FET as a Label-Free Biosensor

In this paper, we propose and simulate a charge-plasma (CP)-based dielectrically modulated (DM) source-engineered Schottky barrier field-effect transistor (SE-SB-FET) as a device for biomolecule sensing. The proposed device employs metal silicide (ErSi1.7) as source/drain regions and Hafnium (workfunction = 3.8 eV) as dual metallic source extensions. The oxide below the source extensions are etched out to create two horizontal L-shaped nanogap cavities for biomolecule detection. The presence of biomolecules is characterized by the change in dielectric constants and the associated charge densities, which, in turn, modulates the Schottky barrier (SB) width at the source-channel (metal/Si) junction, owing to the formation of an electron-CP in an undoped-Si film. A comparative analysis of the SE-SB-FET and the conventional DM-FET in terms of sensitivity has been performed as a function of dielectric constant ( ${K}$ ) and the associated charge density ( $\rho $ ), along with the thickness ( ${T}_{\textsf {C}}$ ) and the length ( ${L}_{\textsf {C}}$ ) of the cavity. Furthermore, calibrated simulations reveal that the relative change in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (sensing parameter herein calculated at ${V}_{\textsf {GS}}={V}_{\textsf {DS}}={1}$ V) in SE-SB-FET is much better (maximum of ${3}\times $ for neutral; ${2.9} \times $ for charged biomolecules at $\rho =-{1}\times {10}^{{11}}$ cm $^{-{2}}$ ). We further observe a significant improvement in sensitivity at low temperature ( $25\times $ at ${K}={5}$ ; $\rho ={0}$ at 100 K). Thus, SE-SB-FET biosensor provides better sensing capability for biomolecule detection when compared to the conventional DM-FET biosensor.

Intrinsic Performance of Germanane Schottky Barrier Field-Effect Transistors

Germanane (GeH), a hydrogenated germanium monolayer, is a new family of 2-D semiconductors, exhibiting promising potential for electronic device applications. Here, we investigate GeH Schottky barrier (SB) field-effect transistors (FETs) using atomistic quantum transport simulations. Our simulation results reveal that the ohmic-contact device with zero SB height ( $\Phi _{\text {Bn}}$ ) exhibits ~20% lower ON-current than the metal-oxide-semiconductor (MOS) FET counterpart due to the inherent tunnel barrier at the metal–semiconductor junction. We also compare 14-nm-channel GeH and black phosphorus (BP) SBFETs with a finite SB height of $\Phi _{\text {Bn}} = 0.22$ eV for both devices. Our results show that GeH outperforms BP in the ON-state, but it can suffer from larger leakage current in the OFF-state. We further investigate the effect of barrier height in GeH SBFET by varying $\Phi _{\text {Bn}}$ from 0 eV to a half bandgap (0.78 eV). In general, as barrier height increases, both ON-current and the minimum leakage current are reduced. It is also observed that, with increasing SB height, intrinsic delay increases but the required energy per switching decreases, indicating the trade-off between the device speed and the energy dissipation. Our benchmarking of GeH SBFET against GeH and BP MOSFETs demonstrates that GeH generally outperforms BP in terms of energy-delay product (EDP). By performing careful engineering of SB height along with the device threshold voltage, we show that the minimum EDP of GeH SBFET can be as comparable as that of the MOSFET counterpart, suggesting great potential of GeH SBFETs for future switching device applications.

Improving Performances of In-Plane Transition-Metal Dichalcogenide Schottky Barrier Field-Effect Transistors.

Monolayer Schottky barrier (SB) field-effect transistors based on the in-plane heterojunction of 1T/1T'-phase (metallic) and 2H-phase (semiconducting) transition-metal dichalcogenides (TMDs) have been proposed following the recent experimental synthesis of such devices. By using density functional theory and ab initio simulations, intrinsic device performance, sub-10 nm scaling, and performance boosting of MoSe2, MoTe2, WSe2, and WTe2, SB field-effect transistors are systematically investigated. We find that the Schottky barrier heights (SBHs) of these in-plane 1T(1T')/2H contacts are proportional to their band gaps: the bigger band gap corresponds to bigger SBH. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T'/2H contact. The WTe2 SB field-effect transistor can provide the best performance and satisfy the requirement of the high-performance transistor outlined by the International Technology Roadmap for Semiconductors down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the source/drain regions can modulate conduction band SB, leading to the 8.8 nm WSe2 SB field-effect transistor also satisfying the requirement. Moreover, the introduction of the underlap can increase the effective channel length and reduce the coupling between the source/drain and the channel, leading to the 5.1 nm WTe2 SB field-effect transistor also satisfying the International Technology Roadmap for Semiconductors high-performance requirement. The underlying physical mechanisms are discussed, and it is concluded that the in-plane SB engineering is the key point to optimize such two-dimensional devices.