Schmitt Trigger Research Articles

Design of reliable and fast Schmitt trigger 10T SRAM cells using in-memory computing

Abstract Microprocessors, integrated data storage systems, and cache memories are just a few applications that can benefit from Static random access memory (SRAM). Computing In memory provides a solution for the von Neumann bottleneck problems. Simultaneously, it removes needless repeated data transmission between CPU and memory. Schmitt trigger was utilized for energy-efficient operation to get high reading and writing capacity. Two cross-coupled inverters with a transistor in between increase the design writing process. Furthermore, voltage boost logic is prioritized to maximize the node capacity. Using two dummy columns and dummy rows in RAM, the Replica technique controls the flow of signals via the core. The simulated results are compared to the designs that already exist. The simulation results show that the leakage power of the proposed design is 0.75 nw at 0.6 volts. The write static noise margin (WSNM) of the proposed cell is twice that of SEDF10T, which can be helpful for high-performance computing applications.

Lithium Solid Electrolyte-Gated Oxide Transistors-Based Schmitt Trigger With High Thermal Resistance

Lithium Solid Electrolyte-Gated Oxide Transistors-Based Schmitt Trigger With High Thermal Resistance

Bistable organic electrochemical transistors: enthalpy vs. entropy

Organic electrochemical transistors (OECTs) underpin a range of emerging technologies, from bioelectronics to neuromorphic computing, owing to their unique coupling of electronic and ionic charge carriers. In this context, various OECT systems exhibit significant hysteresis in their transfer curve, which is frequently leveraged to achieve non-volatility. Meanwhile, a general understanding of its physical origin is missing. Here, we introduce a thermodynamic framework that readily explains the emergence of bistable OECT operation via the interplay of enthalpy and entropy. We validate this model through temperature-resolved characterizations, material manipulation, and thermal imaging. Further, we reveal deviations from Boltzmann statistics for the subthreshold swing and reinterpret existing literature. Capitalizing on these findings, we finally demonstrate a single-OECT Schmitt trigger, thus compacting a multi-component circuit into a single device. These insights provide a fundamental advance for OECT physics and its application in non-conventional computing, where symmetry-breaking phenomena are pivotal to unlock new paradigms of information processing.

Design of Fluxgate Current Sensor Based on Magnetization Residence Times and Neural Networks.

This study introduces a novel fluxgate current sensor with a compact, ring-shaped configuration that exhibits improved performance through the integration of magnetization residence times and neural networks. The sensor distinguishes itself with a unique magnetization profile, denoted as M waves, which emerge from the interaction between the target signal and ambient magnetic interference, effectively enhancing interference suppression. These M waves highlight the non-linear coupling between the magnetic field and magnetization residence times. Detection of these residence times is accomplished using full-wave rectification circuits and a Schmitt trigger, with a digital output provided by timing sequence detection. A dual-layer feedforward neural network deciphers the target signal, exploiting this non-linear relationship. The sensor achieves a linearity error of 0.054% within a measurement range of 15 A. When juxtaposed with conventional sensors utilizing the residence-time difference strategy, our sensor reduces linearity error by more than 40-fold and extends the effective measurement range by 150%. Furthermore, it demonstrates a significant decrease in ambient magnetic interference.

Global RC Interconnects with ADL Buffers for Low-Power Applications

Introduction: Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem. Methods: With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL). Results: To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit. Conclusion: The suggested model's performance is compared to that of other cutting-edge methods.

A Novel Dual-Mode Dual Type Hysteresis Schmitt Trigger and its Applications using Single Differential Voltage Current Conveyor Transconductance Amplifier

A Novel Dual-Mode Dual Type Hysteresis Schmitt Trigger and its Applications using Single Differential Voltage Current Conveyor Transconductance Amplifier

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

A High-Efficiency, Ultrawide-Dynamic-Range Radio Frequency Energy Harvester Using Adaptive Reconfigurable Technique

This paper presents a novel adaptive reconfigurable rectifier architecture for radio frequency energy harvesting (RFEH); in addition, a new metric for high-efficiency dynamic range (DR) is proposed. The presented rectifier architecture is based on a double-sided diode-feedback cross-coupled differential-drive rectifier (CCDR) structure incorporating self-body bias for reconfigurable operation. An adaptive structure based on a Schmitt trigger is proposed to adaptively switch the rectifier connection without auxiliary voltage (Vaux), with two rectifier stages in parallel at low power and in series at high power. The system is simulated at a 180 nm CMOS process and the results show more than 17 dB DR at 900 MHz, with efficiency higher than 50% at a 100 kΩ load.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

A Reliable and high performance Radiation Hardened Schmitt Trigger 12T SRAM cell for space applications

In the vacuum of space, alpha particles and cosmic radiation can cause the node data to be altered, leading to data loss. When a radiation particle hits a vulnerable point of the typical 6T static random access memory (SRAM) cell, it results in the alteration of the stored data within the cell, leading to a single-event upset (SEU). Traditional 6T SRAM cannot withstand the extreme conditions present in space. Hence, it is imperative to develop an SRAM that can endure these challenging space conditions. To address the impact of SEUs, a Radiation Hardened Schmitt Trigger 12 transistor (RHST12T) SRAM cell is proposed in this paper. To gauge the comparative effectiveness of the proposed cell, it is compared with other radiation hardened SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, and SRRD12T. Even if a radiation strike flips the node values, all of RHST12T sensitive nodes can recover their data. It shows up to 1.6×/45.32×/0.29 ×106× less read delay, write delay, and leakage power consumption, respectively as compared to other considered SRAM cells. It achieves up to 5.75×/3.09× better read and hold stability, respectively than the considered SRAM cells.

Optoelectronic devices based on configurable hysteresis of Schmitt trigger circuit control with the employment of CMOS technology

Optoelectronic devices based on configurable hysteresis of Schmitt trigger circuit control with the employment of CMOS technology

A reverse Schmitt trigger with an adjustable hysteresis window implemented by mesoporous silica electrolyte-gated transistors

The development of low-voltage, low-power Schmitt triggers will help in further optimizing the performance of portable and wearable electronic devices.

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems

A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems

Noninverting Schmitt trigger circuit with electronically tunable hysteresis

This paper reports a tunable hysteresis CMOS Schmitt trigger design techniques and an investigation of new buffer-based designs. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage tune controlled sourcing transistor, the hysteresis window can be easily changed. Moreover, the new designs are immune to the kick-back noise coming from the succeeding inverter blocks. In this work, the VT-ST proves itself more reliable regarding dynamic and leakage power consumption and propagation delay. In this work, aspect ratio of the transistors is kept as small as possible, and the hysteresis loop is varied with a tunable voltage transistor. 5000 Monte Carlo simulations reveal that the VT-ST is more reliable as ΔVLHandΔVHL are almost equal, and a small variation is observed. For the comprehensive analysis, a figure of merit for all the circuits is derived and it is 3.16× higher for the proposed VT-ST than the conventional circuit. All simulation work is handled by the cadence virtuoso tool using UMC 40 nm technology.

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Efficient design approaches to model CNTFET-based Ternary Schmitt Trigger circuits

Digital computation using radix three offers the benefit of increased information density with less power consumption due to reduced interconnect complexity. Hence this brief presents two architectures for ternary Schmitt trigger designs that are implemented by combining shifting literals, ternary inverters and decoder equivalents using carbon nanotube technology. In the first proposed design, Schmitt trigger hysteresis curves are realized using shifting literals i.e. successor and predecessor cells. The second proposed design employs ternary inverters and a decoder equivalent of intermediate logic level for the implementation. The experimental analysis involves the simulations that are conducted using HSPICE and the standard Stanford CNTFET model. Simulation results confirm that the proposed ternary Schmitt trigger designs outperform in terms of power consumption and power delay product(PDP), showcasing the power reduction average of 75% and PDP reduction average of 79% respectively in comparison to recent counterparts. Moreover, Monte Carlo simulations are conducted to verify the robust operation of proposed designs and lesser deviations are observed in performance parameters towards process variations.

-Memory Computing Based Reliable and High Speed Schmitt trigger 10T SRAM cell design

Static random access memories (SRAM) are useful building blocks in various applications, including cache memories, integrated data storage systems, and microprocessors. The von Neumann bottleneck difficulties are solved by in-memory computing. It eliminates unnecessary frequent data transfer between memory and processing units simultaneously. In this research, the replica-based 10T SRAM design for in-memory computing (IMC) is designed by adapting the word line control scheme in 14nm CMOS technology. In order to achieve high reading and writing capability, the Schmitt trigger inverter was used for energy-saving and stable use. To speed up the writing process of the design, a single transistor is inserted between the cross-coupled inverters. In addition, to increase the node capacity, the voltage boosting circuitry is emphasized. The adaptive word line control scheme was utilized by integrating the replica column based circuit. The Replica approach regulates signal flow through the core by using a dummy column and a dummy row in RAM. To demonstrate the viability of the suggested design, the simulated outcomes are contrasted with those of existing designs. The various performance metrics examined are Read Static Noise Margin (RSNM), Write (WSNM), Hold (HSNM), Read Access Delay (RAD), Write Access Delay (WAD), Read performance and Write performance the varying supply voltage is evaluated.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Soft Error Simulation of Near-Threshold SRAM Design for Nanosatellite Applications

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit.

Two MOS transistor based floating memristor circuit and its application as oscillator

This research article reports a novel off–the-shelf floating memristor circuit based on MOS transistor. The proposed memristor circuit comprises one NMOS, one PMOS and a constant current source. The designed circuit utilized intrinsic parasitic capacitance instead of conventional metal plate capacitor. Pinch hysteresis curve of the designed memristor is maintained for range of frequencies from 380 kHz to 1 GHz. Parameters of the proposed circuit may be tuned by varying the bias current of current source. Performance of the proposed circuit is verified by SPICE simulator using 0.18 µm CMOS technology parameter. In addition, Process corner variation, temperature variation, supply voltage variation and variation in size of transistor are investigated to justify the robustness of the designed circuit. Total power consumption of the designed memristor is 4 µW. Chip area of the proposed circuit is 336.55 µm2. Moreover, applications of the proposed circuit are well described with memristor based Schmitt Trigger circuit and Wien Bridge oscillator circuit.