Schmitt Trigger Circuit Research Articles

Optoelectronic devices based on configurable hysteresis of Schmitt trigger circuit control with the employment of CMOS technology

Optoelectronic devices based on configurable hysteresis of Schmitt trigger circuit control with the employment of CMOS technology

Noninverting Schmitt trigger circuit with electronically tunable hysteresis

This paper reports a tunable hysteresis CMOS Schmitt trigger design techniques and an investigation of new buffer-based designs. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage tune controlled sourcing transistor, the hysteresis window can be easily changed. Moreover, the new designs are immune to the kick-back noise coming from the succeeding inverter blocks. In this work, the VT-ST proves itself more reliable regarding dynamic and leakage power consumption and propagation delay. In this work, aspect ratio of the transistors is kept as small as possible, and the hysteresis loop is varied with a tunable voltage transistor. 5000 Monte Carlo simulations reveal that the VT-ST is more reliable as ΔVLHandΔVHL are almost equal, and a small variation is observed. For the comprehensive analysis, a figure of merit for all the circuits is derived and it is 3.16× higher for the proposed VT-ST than the conventional circuit. All simulation work is handled by the cadence virtuoso tool using UMC 40 nm technology.

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Design and Evaluation of Low Power CMOS Based Schmitt Trigger Circuits

Efficient design approaches to model CNTFET-based Ternary Schmitt Trigger circuits

Digital computation using radix three offers the benefit of increased information density with less power consumption due to reduced interconnect complexity. Hence this brief presents two architectures for ternary Schmitt trigger designs that are implemented by combining shifting literals, ternary inverters and decoder equivalents using carbon nanotube technology. In the first proposed design, Schmitt trigger hysteresis curves are realized using shifting literals i.e. successor and predecessor cells. The second proposed design employs ternary inverters and a decoder equivalent of intermediate logic level for the implementation. The experimental analysis involves the simulations that are conducted using HSPICE and the standard Stanford CNTFET model. Simulation results confirm that the proposed ternary Schmitt trigger designs outperform in terms of power consumption and power delay product(PDP), showcasing the power reduction average of 75% and PDP reduction average of 79% respectively in comparison to recent counterparts. Moreover, Monte Carlo simulations are conducted to verify the robust operation of proposed designs and lesser deviations are observed in performance parameters towards process variations.

Two MOS transistor based floating memristor circuit and its application as oscillator

This research article reports a novel off–the-shelf floating memristor circuit based on MOS transistor. The proposed memristor circuit comprises one NMOS, one PMOS and a constant current source. The designed circuit utilized intrinsic parasitic capacitance instead of conventional metal plate capacitor. Pinch hysteresis curve of the designed memristor is maintained for range of frequencies from 380 kHz to 1 GHz. Parameters of the proposed circuit may be tuned by varying the bias current of current source. Performance of the proposed circuit is verified by SPICE simulator using 0.18 µm CMOS technology parameter. In addition, Process corner variation, temperature variation, supply voltage variation and variation in size of transistor are investigated to justify the robustness of the designed circuit. Total power consumption of the designed memristor is 4 µW. Chip area of the proposed circuit is 336.55 µm2. Moreover, applications of the proposed circuit are well described with memristor based Schmitt Trigger circuit and Wien Bridge oscillator circuit.

A new passive non-ideal floating memristor emulator circuit

A new passive non-ideal floating memristor emulator circuit (MEC) is proposed in this paper. The MEC is only composed of four transistors, two resistors, and one capacitor. The circuit needs no external bias. Transistors control the direction of current conduction, changing the resistance state of the circuit, while capacitors make the circuit exhibit hysteresis characteristics. The V-I curve of the circuit exhibits the Type-II memristive hysteresis loop. The validity of the theoretical study is demonstrated by simulation results using the Cadence design environment with 0.18 μm SMIC technology. Additionally, the proposed MEC has been tested in the Schmitt trigger circuit and amplitude demodulation circuit, proving that it can be used in practical applications.

SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node

Compared with bulk technologies, Fully-depleted silicon-on-insulator (FD SOI) technology nodes show better resistance to single-event upsets. However, additional hardening techniques should be investigated to mitigate upsets at this technology node. Single-event (SE) performance of multiple hardened flip-flop (FF) designs based on Schmitt-trigger circuits along with a conventional DFF design in a 22-nm FD SOI process is presented. FF designs were tested using alpha particles and heavy-ions. Results show significant reductions in SEU cross-sections compared with the conventional design. Alpha particle exposures showed zero upsets for all FF designs tested. Schmitt-trigger-based FF designs showed from 2× to 200× improvement in heavy-ion SEU cross-sections compared with the conventional DFF design.

Experimental Investigation of Microcontroller-Based Acoustic Temperature Transducer Systems

Temperature transducers are commonly used to monitor process parameters that are controlled by various types of industrial controllers. The purpose of this study is to design and model a simple microcontroller-based acoustic temperature transducer based on the variations of resonance conditions in a cylindrical resonance tube. The transducer's operation is based on the generation of an acoustic standing wave in the free resonance mode of generation within a cylindrical resonance tube which is converted into a train of pulses using Schmitt trigger circuit. The frequency of the generated standing wave (i.e., the train of pulses) is measured by the Arduino Uno microcontroller, where a digital pin is used to acquire pulses that are counted using a build-in software function in an Arduino IDE environment. Experimental results are performed for three sizes of diameters to investigate the effect of the diameter of resonance tube on the obtained results. The maximum nonlinearity error according to Full-Scale Deflection (FSD) is about 2.3 percent, and the relative error of the transducer is evaluated using experimental findings and the regression model. The circuit simplicity and design of the suggested transducer, as well as the linearity of its measurements, are notable.

A compact floating and grounded memristor model using single active element

Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.

Analysis of a Low Power Inverting CMOS Schmitt Trigger Operating in Weak Inversion

This article analyzes the operation of a low power inverting CMOS Schmitt trigger in weak inversion. The analysis is based on an earlier proposed analytical model, which relates the hysteresis voltages to the transistors' dimensions, the supply voltage, and the temperature. The maximum error between the analytical and simulated transition voltages is below 10%, relative to the supply voltage. By optimizing the device sizes, the error reduces to 4%. The operation of the Schmitt trigger in weak inversion is also experimentally validated through an ASIC fabricated in AMS 0.35μm CMOS process. The maximum error between the modeled and measured transition voltages is below 7%. Furthermore, the power consumption as a function of the supply voltage is analyzed. Overall, the proposed model may be used to optimize the operation of the analyzed Schmitt trigger circuit for low power operation.

Compact Programmable True Random Number Generator Based on Spin Torque Nano-Oscillator

True Random Number Generator(TRNG) is the key component for stochastic computation. It can also act as the Probabilistic Bit(P-Bit) which is the core device for Ising Computer. In previous study, we have proposed a novel programmable TRNG based on Spin Torque Nano-Oscillator(STNO). With this TRNG constructed with STNO, a time division multiplexing Ising computer is designed to work under the Incremental Coupling Rule. However, the programmable TRNG is still lack of a corporeal hardware implementation. In this work, a SPICE model for STNO which can accurately describe the frequency, resistance as well as noise spectrum is provided first. And then, a compact optimized Schmitt trigger circuit with 14 nm FinFET technology is proposed to construct the programmable TRNG. Finally, the performance of the compact programmable TRNG circuit is evaluated and discussed.

Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications

The internet of things (IoTs)-based systems require battery-enabled energy-efficient memory circuits to operate at low voltage domain, especially below the transistor’s threshold. This study presents a single-ended 7T SRAM cell for IoTs applications. Cell core of the proposed 7T SRAM cell is composed of a novel Schmitt-trigger circuit in which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. The proposed 7T SRAM cell employs only one bitline to perform both read and write operations to reduce active power consumption. Read operation of the proposed 7T SRAM cell is conducted using only a single n-type MOSFET transistor driven by QB node. This transistor isolates bitline from storage nodes during read operation, improving read stability (RSNM) and read delay (TRA). A p-type MOSFET controlled by write wordline is placed inside the cell core to cut its feedback path off during write operation. This mechanism eliminate writing ‘1′ issue in single-ended SRAM cell and facilitate write ‘1′ operation, resulting in write-ability (WSNM) enhancement. To prove superiority of the proposed 7T SRAM cell in the various design metrics, it is compared with six state-of-the-art SRAM cells at subthreshold supply of VDD = 0.3 V. The proposed 7T SRAM cell is the second/first/third best cell in terms of RSNM/WSNM/write access time (TWA). Furthermore, an improvement of at least 2.55X in TRA and 12.58X (2.02X) in read (write) energy consumption is achieved by the proposed 7T SRAM cell. Although, the proposed 7T SRAM cell offers some disadvantages, nevertheless it offers the best proposed figure of merit.

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

Inadequacy of the classical formulation of the CMOS Schmitt trigger

SummaryThe classical complementary metal–oxide–semiconductor (CMOS) Schmitt trigger (ST) circuit operating in strong inversion has been used as a basic building block in electronics since the 70s. However, no appropriate analytical models for determining the hysteresis threshold voltages have been presented. In this paper, we review the classical CMOS ST formulation for operation in strong inversion and introduce a new model for calculating the hysteresis window. In order to validate the approximations employed in this work, we measured the hysteresis curve for several combinations of transistors available in the popular off‐the‐shelf CD4007 and resorted to simulation in a 180‐nm technology for the specific purpose of measuring the ST window in terms of the transistors aspect ratios. Numerical, experimental, and simulation results corroborate the approximations employed in this research to derive simple expressions for the hysteresis threshold voltages.

BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit

This letter presents a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage. An only NMOS transistor is used in the proposed VB-ST circuit, which helps to reduce the aging effect specially Negative Bias Temperature Instability (NBTI) on the circuit. The reliability of the circuit is mainly analyzed by using the critical charge and soft error rate ratio (SERR), which indicates that the critical charge and SERR of the VB-ST circuit are improved by $6.31\times $ and reduced by 84.0%, respectively as compared to the CMOS circuit at 0.4V supply voltage. For the reliable and robust proposed circuit design, the quality factor (QF) is used as a performance metric and observed that the proposed circuit has $144\times $ improved QF as compared to the CMOS circuit.

Novel approaches for quickly measuring engine speed applied to gasoline engine diagnostics

The parameter of engine speed plays an important role to recognize the engine's condition while working. By using this parameter, it is possible to diagnose engine's malfunctions. In this study, in case of the gasoline engine, we introduce two efficient methods for measuring the engine speed without extracting electrical signals from conventional engine speed sensors. For the first approach, based on the signal pin of the sensor, the engine speed was determined from the frequency of manifold absolute pressure. For the second approach, the frequency of the voltage drop measured at the battery positive terminal caused by ignition operation is the key to calculate the engine speed. The noise filter circuits and the amplifier circuits are used to refine signal, Besides, a Schmitt Trigger circuit using a NE555 timer IC was designed to reshape the oscillation signal from either of these sources into a square wave of which frequency was measured and converted to the engine speed by a microprocessor and display the result on the LCD screen.Compared to engine speed measured by a conventional inductive sensor, the proposed methods provide a competitive result with fast response. The second approach was highly promising due to its simplicity involving in direct voltage measurement at the battery positive terminal.

Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits

Bias Temperature Instability and soft error rate are the major reliability issue with the technology scaling. BTI leads to an increase in the threshold voltage of the MOS transistors, which reduces the drain current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this paper, we propose a novel reliable voltage bootstrapped Schmitt trigger circuit with soft error hardening enhancement and lower effect of BTI. We investigate all the circuit simulations which impact on the soft error rate of inverter circuits using HSPICE 65 nm CMOS technology. The results show that the proposed inverter circuit has a higher critical charge and lower soft error rate (SER) when compared to other reference inverter circuits. To better assess, we introduced Vth sensitivity and observed that the degradation of the proposed inverter circuit is 30% higher as compared to conventional CMOS inverter. The proposed inverter offers lower dynamic power, leakage power, and circuit delay of 91.11%, 93.47%, and 38.17%, respectively, as compared to CMOS inverter at 3 years of the stress time. Finally, the overall circuit performance is evaluated using the figure of merits and observes that the proposed inverter has the highest FOM correspond to other inverter circuits, which reveal that the proposed circuit is useful for the applications where the effect of radiations are higher.

Design and analysis the operation of Schmitt trigger circuit in radiation environment

The object of research is the effect of gamma radiation on the characteristics of the operation amplifier, and consequently the behavior of the output voltage waveforms of Schmitt trigger circuit. One of the most problematic is the effect of the circuit elements, reference voltage, input frequency, input DC-voltage and bias voltage effects, on the operation of the proposed Schmitt trigger circuit. In the course of the research, the used Op Amp can be exposed to different types of radiation. As a result of the research it is shown that the threshold levels of Schmitt trigger circuit increased when operates in nuclear radiation environment.From the experimental work, computer simulation, and results analysis, the conclusions could be deduced, that Operation of operational amplifiers in gamma radiation environment show serious changes on their electrical characteristics. As a result, the Schmitt trigger circuit exposed to gamma radiation range from 3 kGy up to 20 kGy, at 10 Hz, where, its output voltage waveforms are shown to be independent on the gamma-dose. On the other hand, at frequency of 4.0 kHz, a severe effect are noticed, where the lower threshold level (VLTL) increase from –5.35 V up to –3.58 V, while the upper threshold voltage level (VUTL) is slightly increased from 4.21 V to 5 V, as a function of the same gamma doses. The obtained experimental results are shown to be in close agreement with those obtained from programming the Schmitt trigger equations to computer.In the future, the proposed approaches show that, whenever the Op Amp circuits are used in gamma radiation environment, it preferable to be operate at low frequency levels, where the output voltage waveform of Schmitt trigger circuit are shown to be independent on gamma dose but at high frequency the effect increased as a function of same gamma dose.

An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger

This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion: Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.