CMOS Technology Scaling Research Articles

Radiation-hardened latch design with triple-node-upset recoverability

As CMOS technology scales down the susceptibility of integrated circuits to radiation effects makes them vulnerable to single-event upsets (SEUs) that may cause the formation of soft errors. In nanometer technologies, SEUs have the potential to impact many nodes within a circuit, resulting to Multiple Node Upsets (MNUs). Several techniques have been proposed to deal with SEUs that simultaneously influence either one, two, or three nodes. This paper presents a latch design that is capable of tolerating up to triple-node upsets (TNUs). Hardware redundancy is exploited to store data in many nodes inside the latch, along with a multiple feedback scheme that provides the recovery of the correct latch state in the case of SEUs. The proposed method provides faster recovery time after an SEU, and at the same time reduced power-delay and area-power-delay products with respect to existing solutions in the literature.

(Invited) Material Engineering for the GAA and Post-GAA Transistors and Interconnects

Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC.Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability.Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology. The next transition, from GAA to the NMOS and PMOS GAA transistors stacked on top of each other (often referred to as CFET (Complementary Field Effect Transistor)) is expected in 8 to 10 years from now.The main methodology for GAA and CFET transistor engineering comes down to bandstructure engineering, where material composition, shape and thickness of different layers, and mechanical stress are engineered to tailor a bandstructure of the channel that maximizes on-state driving strength and minimizes off-state leakage and variability. The key methodology for bandstructure engineering is ab-initio analysis of transistor components and then transfer of the obtained bandstructure to transistor scale analysis to characterize its behavior.For the interconnect engineering, the tight metal pitches and increasingly tall and narrow vias dictate transition from copper to alternative metals, with a preference for the metals that can be etched and selectively grown. The key methodology for interconnect engineering is ab-initio analysis of electron scattering at the interfaces and grain boundaries. The scattering is then converted into interconnect resistance that defines speed and power consumption of the advanced CMOS circuits.This work introduces the concepts of transistor band structure engineering and interconnect scattering engineering and provides illustrations of these methodologies applied to GAA and post-GAA technologies.

Impact of PVT Variations on Optimizing Silicon Power

The scaling of CMOS technology faces challenges as the demand rises, but FinFETs emerging as a vital alternative for 22nm technology node and lower. Otherwise, FinFETs tend to have multiple PVT variations, making static timing analysis (STA) more flexible and suitable to analyze the timing delay of the logic generation. Device simulation and statistical temporal analysis are used to derive PVT variation models for FinFET-based standard cell designs. Mixing different FinFET design styles shows promise in optimizing delays and leakage, as FinFETs offer better control of short-channel effects and processing scalability. Furthermore, lowering clock skew is also a prime design aspect to consider. However, as technology scales to smaller devices, process, voltage, and temperature (PVT) variations make minimizing clock distortion very difficult. To mitigate the effects of PVT variations, many previous works proposed a Post Silicon Tuning (PST) architecture to dynamically balance the skew of the clock tree. In this paper, we will disclose the details of clock tree synthesis optimizations and FinFET logic developments minimizing PVT variations.

Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights

In the evolution of integrated circuit technology, chip size and performance enhancement stand as paramount and challenging domains of progress. Yet, a dearth of foundational simulations and comparisons for introductory purposes exists. Consequently, this study delves into an introduction of distinct advanced integrated circuit (IC) technologies: CMOS, FinFET, and CNTFET, dissecting their merits and limitations. Subsequently, a preliminary simulation is executed to authenticate specific characteristics inherent to these IC technologies. Discoveries indicate that as IC transistors scale down, there are marked improvements in transistor performance, encompassing aspects such as switching speed, noise immunity, power efficiency, and heat dissipation. Further, a simulation grounded on a NAND gate substantiates certain traits in CMOS and FinFET, specifically switching speed, propagation delay, and noise margin. The results illustrate a superior performance of FinFET over CMOS. Additionally, as CMOS technology scales, its efficacy enhances. Nonetheless, the present research and simulations hold potential uncertainties and constraints, paving avenues for more refined investigations in the future.

Design and implementation of a Low power Adder Circuit Using LECTOR Technique

This work implements a 1-bit FA circuit with the CMOS logic with XOR-XNOR combinations. For sum and carry, pass transistors are used to generate the output by combining with XOR, XNOR and CMOS design, and the optimised full adder is implemented with the help of LECTOR technique to control the leakage power. As scaling of CMOS technology has shown improvement in the speed but the leakage power are left to act as major effect. low power VLSI is a new discipline in which high power consumption is becoming an important criteria. But when refers to battery life, high power dissipation is not recommended for device applications. It affects performance, raises cooling expenses, and shortens battery capacity. The switching, dynamic and leakage power changes the inputs significantly. There are several typical reduction strategies available to lower the energy of circuits. By implementing the reduced FA with the leakage power control technique the number of transistors reduced than the normal full adder. The proposed design has static and total power of 5.08nw and 8.33uw for XNOR and for XOR of 12.36nw and 8.56uw. A FA is designed using these technique the obtained results for static and total power are 12.38uw 8.58uw. For the above circuits, a comparison of various static and total power dissipations is conducted. CADENCE-VIRTUOSO is used to simulate circuits using 90nm technology with a 1.2V power supply.

Compressed Sensing Σ-Δ Modulators and a Recovery Algorithm for Multi-Channel Wireless Bio-Signal Acquisition

Compressed sensing (CS) exploits signal sparsity in some domain to enable sub-Nyquist sampling which increases the energy efficiency of analog-to-digital conversion (ADC) and downstream data processing circuits–the sampling frequency is determined by the information rate, not the usual Nyquist rate. CS techniques for wireless multi-channel bio-signal recording applications based on sigma-delta modulation (SDM) are detailed and used to validate a multi-channel recovery algorithm. The SDM topology allows the required dot product calculations between the measurement and signal vectors to be performed in conjunction with its inherent integration using minimal additional circuitry. It eliminates opamp output saturation concerns and benefits directly from still ongoing Moore’s Law CMOS technology scaling. Finally, a sparse sensing matrix and recovery algorithm are described that exploit similar sparse signatures across multiple channels to improve both signal recovery accuracy and chip area efficiency. Simulation results validate the concepts.

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ∼15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ∼3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ∼4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.

The design of a low-power 4-bit barrel shifter for a current steering DAC using optimized multiplexers in 65 nm technology

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

An Intelligent Sensing Framework for Post-Manufacturing Performance Measurement and Healing of CSVCO

With CMOS technology scaling for miniaturization and performance improvement, analog and radio frequency integrated circuits (RFICs) are very much affected by process variations leading to performance degradation. A post-manufacturing healing mechanism with low overhead is desirable to compensate for these variations. A machine learning (ML)-assisted sensing mechanism has been proposed in this work for design of nonintrusive process variation sensor (PVS). Low-cost test signatures (TSs) extracted from these PVS are placed close to the circuit under test (CUT) and this does not load or couple to any nodes of CUT. As the TSs remain invariant with the shifts in control knobs (CKs), performance healing against process variations can be achieved with a single set of extracted TSs. A novel one-step healing approach is proposed in this work for selection of appropriate CK with the help of a neural regression model during the production test in automated test equipment (ATE). The proposed healing approach is illustrated on a current-starved voltage-controlled oscillator (CSVCO) circuit, to recover yield loss due to fabrication process variations.

Design and Implementation of Hybrid DC-DC Converter: A Review

The advancement in Power Management Integrated Circuit (PMIC) has driven the DC-DC conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low power density and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.

Vapor phase synthesis of topological semimetal MoP2 nanowires and their resistivity

Topological semimetals (TSMs) possess topologically protected surface states near the Fermi level with high carrier densities and high mobilities, holding distinct potential for low-dissipation on-chip interconnects that may outperform current copper interconnects for continued dimensional scaling of CMOS technologies. To translate the exotic properties of TSMs into practical interconnects, developments of high precision synthesis for these emergent semimetals are essential. Here, we report the synthesis of TSM molybdenum diphosphide (MoP2) nanowires with controlled dimensions and crystallinity. By varying the growth temperature in chemical vapor depositions (CVD), we achieve polycrystalline MoP2 as well as single-crystalline MoP2−x nanostructures, which are confined in highly anisotropic forms on crystalline substrates with a miscut angle of 1°. The measured metallic properties, such as room temperature resistivity and temperature-dependent resistance, of the synthesized MoP2 nanostructures show promising dimensional effects for interconnect applications, suggesting potential enhancement of topological surface states in electron transport at reduced dimensions. The demonstration of CVD-grown MoP2 nanowires provides opportunities for careful investigations of design rules for TSMs-based nanoscale interconnects.

Crossing the Boundaries between Analogue and Digital

Given that they do not benefit from CMOS technology scaling, analogue integrated circuits are soon becoming a constraint in terms of the cost and performance of nanoscale integrated systems. This has led to some debate about whether analogue circuits are still useful in the era of digital technology. The usual reaction is that analogue circuitry will always be needed, if not everywhere, then at least in interface circuits that exchange data with physically analogue environments. The fact that matter is made up of discrete atoms and molecules, that basic physical quantities like electromagnetic radiation and electric charge are quantized, and even that information is transmitted as discrete pulses in biological systems all make the physical world less "intrinsically analog" than it first appears. In other words, it appears more and more plausible that the foundation for our regular analogue experiences is a distinct or digital one.

Nanowatt Integrated Circuits and Systems [The Editors’ Desk

The scaling of CMOS technology continues to follow Moore&#x2019;s law through clever designs at the transistor, circuit, and system levels, from both manufacturing and packaging. The integration of 50 billion-plus transistors into a single silicon chip has become quite common. Power consumption is now one of the key design factors in advancing nanoelectronics. It is our great pleasure to introduce Prof. Kiat Seng Yeo and Prof. Chao-Sung Lai as the guest editors of this special issue of <i>IEEE Nanotechnology Magazine</i>.

CMOS Automotive Radar Sensors: mm-Wave Circuit Design Challenges

This brief gives an overview of recent advancements in CMOS automotive radar sensors, focusing on the most critical circuit design at mm-wave frequencies. Highly scaled CMOS technologies enable very low-power consumption, reduced costs, and higher data processing capacity and integration compared to state-of-the-art SiGe BiCMOS chip-set solutions commonly adopted in commercial products. The very bottleneck is still represented by the radio front-end due to the challenging requirements of long-range radars. Circuit topologies and design tradeoffs are here discussed with reference to critical building blocks of the mm-wave radar front-end, reporting circuit implementations for a 77-GHz long-range radar sensor in a 28-nm fully-depleted silicon-on-insulator CMOS technology.

Double-node-upset aware SRAM bit-cell for aerospace applications

In aerospace applications, the continuous scaling of CMOS technology makes SRAM cells more and more susceptible to soft errors. To overcome this issue, a radiation-hardened-based (RHBD) 13T SRAM cell has been proposed in this paper. The proposed cell has several benefits over other standard RHBD cells. The proposed cell can not only recover from SNUs induced at any of its sensitive nodes but also from DNUs induced at any of its sensitive node pairs. It has the lowest hold, total power cost, the highest critical charge, moderate area overhead, and better stability. To improve speed, the proposed cell uses a unique feedback path among its internal nodes. Finally, the figure of merit (FOM), SNU probability of failure (POF) comparison of cells validate that the proposed cell is a better choice for sub-nanometer aerospace applications.

Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

With CMOS technology scaling and increased short channel effects, spin-transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS-based logic-in-memory (LIM) designs consume significantly higher energy at scaled supply voltages. To enhance the energy efficiency of LIM circuit designs, this work proposes a hybrid tunnel FET (TFET)/MTJ-based digital circuit design approach at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathbf {DD}} = 0.3$ </tex-math></inline-formula> V. A Schmitt triggered pre-charge sense amplifier (ST-PCSA) with a strong feedback mechanism at the pull-down section is considered in TFET/MTJ-based LIM designs. The proposed LIM-MTJ designs are implemented using 20 nm TEFT technology and perpendicular anisotropy CoFeB/MgO/CoFeB MTJs. Two input and, or, xor logic gates, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> multiplexer, 1-bit magnetic full adder (MFA), 4-bit magnetic ripple carry adder (RCA), and a simple 1-bit magnetic arithmetic and logical unit (M-ALU) are designed, exploring the proposed ST-PCSA-based hybrid TFET/MTJ logic. The proposed ST-PCSA-based hybrid TFET/MTJ LIM designs achieve ~47.2%–55.55% lower energy consumption in comparison with the PCSA-based TFET/MTJ LIM designs. Performance benchmarking with 20 nm FinFET designs demonstrates that the proposed TFET/MTJ LIM designs achieve 11.1%–25.9% lower energy consumption when compared with equivalent FinFET/MTJ-based LIM designs.

Probabilistic Approximate Computing at Nanoscales: From data structures to memories

The slowdown of CMOS technology scaling has placed architectures and algorithms on focus for future performance improvements in nanoscale computing systems. Two promising approaches at algorithmic level are approximate computing (AC) and probabilistic data structures (PDSs) that employ the tolerance of an application to small deviations in the results for reducing the complexity of the hardware implementation. AC focuses on applications that process numerical data and relies mostly on approximate (or inexact) low-level arithmetic operations. Instead, PDSs target categorical data and rely on shared data structures and other higher-level simplifications that introduce probabilistic deviations even when all operations are exact. Both AC and PDSs have been able to dramatically reduce the cost in some applications, but they are so far completely disconnected in the application domains, the abstraction levels, and the research communities. In this article, we introduce probabilistic approximate computing (PAC), a new paradigm to use application tolerance for small deviations to reduce the implementation complexity of data structures and hardware when implemented with nanoscale memory technologies. Its goal is to have data structures on which both AC and probabilistic techniques are used in a synergetic way to improve efficiency, while keeping deviations within acceptable margins.

Functionalized MoS2 Nanoribbons for Intrinsic Cold-Source Transistors: A Computational Study

Power dissipation is a great challenge for continuous size scaling in CMOS technology because of the thermal limitation on the switching rate of conventional transistors. Here, to break the thermal tyranny, we propose a series of intrinsic cold-source field-effect transistors (CS-FETs) with steep slopes based on armchair transition-metal dichalcogenides (TMD) nanoribbons (NRs) (MX2NRs, M = Mo, W; X = S, Se, Te). The edge states of the TMD NRs can filter out the high-energy electrons and break the “Boltzmann tyranny” at room temperature. First-principles calculations unveil the electronic properties of −H, −F, and −H–O terminated MX2NRs with different ribbon widths. Based on quantum transport simulation, −F and −H–O terminated MoS2NRs present FET performance better than that of the −H terminated MoS2NR. A steep subthreshold swing (28 mV/decade) and a large ON/OFF ratio (4 × 105) are obtained for the 12-MoS2NR–F FET with a 5 nm channel length. Moreover, the effects of the ribbon width, channel length, bias voltage, edge roughness, and defects on MoS2NR–F FET performance are also investigated. This work demonstrates edge functionalization as an effective approach to modulate the TMD NRs and guides the design of intrinsic cold-source transistors.

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Specific figures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.

Application-Aware Quality-Energy Optimization: Mathematical Models Enabled Simultaneous Quality and Energy-Sensitive Optimal Memory Design

Energy efficiency is nowadays a well-known principal design goal across all layers of computing systems (e.g., sensors, mobile, cloud). With diminishing benefits from CMOS technology scaling and increasing demands from unprecedented data size, new memory hardware innovation is greatly needed to enhance energy efficiency of computing systems. Recently, quality-aware hardware design techniques have been developed from different stack layers (device/circuit/architecture/system) to enable near-threshold/sub-threshold voltage operation by trading off between quality and power efficiency. Specifically, based on the energy-quality trade-off and application requirement, memory hardware is designed for the work mode with maximum quality first (step1-design for the work mode) and then the supply voltage will be adjusted in the sleep mode with just-enough quality to achieve maximum efficiency (step2-adjust in the sleep mode). We first propose mathematical models for this two-step design method to avoid time-consuming and laborious ASIC design iterations in traditional hardware design process. However, such a two-step design method focuses more at the application quality than the energy efficiency in all cases. In addition, as the supply voltage in the second step depends on the design from the first step, the solution space of the second step may be greatly limited, far from the true minimum supply voltage. To handle these issues, we propose a new design concept, the simultaneous quality and energy-sensitive optimal design (SQEOD), in which the two objectives are considered simultaneously rather than by two separate steps. By introducing a system-wised importance weight parameter in the modeling process, our method demonstrates system-specific SQEOD mathematical models for different memory designs with various requirements on the application quality and/or energy efficiency. The results of the numerical studies on embedded memory design show that the proposed models provide a useful and fast tool to enable the optimal hardware designs.