Abstract
With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.
Highlights
Dipartimento di Ingegneria Elettronica e Telecomunicazioni (DIET), Sapienza Università di Roma, Abstract: With the continuous scaling of CMOS technology, which has reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits
Being Standard Cell Delay-based Precharge Logic (SC-Delay-based Dual-rail Pre-charge Logics (DPLs) (DDPL)) based on the Time Enclosed Logic (TEL) protocol, we focus on the investigation and analysis of its resilience against attacks exploiting static power (AESP)
Logic, Wave Dynamic Differential Logic (WDDL), MDPL (the MDPL core requires randomness that we generated by means of a linear-feedback shift register, used as Pseudo-Random Number Generator (PRNG)) and SC-DDPL, in order to compare their resistance against AESP and extend the analysis in [13]
Summary
Dipartimento di Ingegneria Elettronica e Telecomunicazioni (DIET), Sapienza Università di Roma, Abstract: With the continuous scaling of CMOS technology, which has reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In SCA, an adversary would not leverage mathematical weaknesses of a cryptographic algorithm to recover sensible data, while making use of physical emissions, or side channels, directly from the device, such as power consumption [2], execution time [1]. In addition to the technological problem due to static power consumption, an Academic Editor: Jim Plusquellic
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