Scalable Parallel Architecture Research Articles

A Parallel Architecture for the Partitioning Around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare.

Clustering is the most common method for organizing unlabeled data into its natural groups (called clusters), based on similarity (in some sense or another) among data objects. The Partitioning Around Medoids (PAM) algorithm belongs to the partitioning-based methods of clustering widely used for objects categorization, image analysis, bioinformatics and data compression, but due to its high time complexity, the PAM algorithm cannot be used with large datasets or in any embedded or real-time application. In this work, we propose a simple and scalable parallel architecture for the PAM algorithm to reduce its running time. This architecture can easily be implemented either on a multi-core processor system to deal with big data or on a reconfigurable hardware platform, such as FPGA and MPSoCs, which makes it suitable for real-time clustering applications. Our proposed model partitions data equally among multiple processing cores. Each core executes the same sequence of tasks simultaneously on its respective data subset and shares intermediate results with other cores to produce results. Experiments show that the computational complexity of the PAM algorithm is reduced exponentially as we increase the number of cores working in parallel. It is also observed that the speedup graph of our proposed model becomes more linear with the increase in number of data points and as the clusters become more uniform. The results also demonstrate that the proposed architecture produces the same results as the actual PAM algorithm, but with reduced computational complexity.

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN’s connectivity, to compile the neuron-synapse model and to monitor SNN’s activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.

A Scalable Parallel Architecture Based on Many-Core Processors for Generating HTTP Traffic

The past years have witnessed the significant development of the Internet. Numerous emerging network architectures and protocols have triggered the demand for traffic generators which stand in stark contrast to previous schemes. Namely, fixed test content is inefficient in the presence of such a dynamic and realistic demand. Moreover, the requirement of high-performance has raised the stakes on developing a new concurrent system. In this paper, we present a hierarchical parallel design for a Web traffic generator on a TILERAGX36 processor, called TGMP. We discuss the challenges in developing its hierarchical architectural design, and elaborate on its implementation details. Specifically, in order to generate a realistic network workload over a long and large time scale, we propose a user-control scheme based on cubic spline interpolation. To better improve the scalability of the system and satisfy the required flow rate, we adopt techniques, including optimization of parameters under the Linux kernel, event-driven concurrency, and parallel architectures of a TILERAGX36 processor. The experimental results demonstrate that TGMP is able to create real traffic and simulate 50,000 users accessing the Web server simultaneously.

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length $N$ could be derived from a pair of DCTs of length $(N/2)$ at the cost of $N$ additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, $N>8$ . We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method.

Biswapped networks: a family of interconnection architectures with advantages over swapped or OTIS networks

We propose a new family of communication architectures called ‘biswapped networks’. Given any n-node basis network Ω, the associated biswapped network Bsw(Ω) is built of 2n copies of Ω, using a simple rule for connectivity that ensures desirable attributes, including regularity, modularity, fault tolerance, and algorithmic efficiency. In particular, if Ω is a Cayley digraph, then so is Bsw(Ω). Our biswapped connectivity provides a systematic scheme for synthesizing large, scalable, modular, and robust parallel architectures. Furthermore, many desirable attributes of the underlying basis network Ω are preserved, as the Bsw(Ω) parameters are related to the corresponding parameters of Ω. We obtain a number of results on internode distances, Hamiltonian cycles, optimal routing, and node-disjoint paths for Bsw(Ω). We explore the relations between biswapped and swapped or optical transpose interconnection system (OTIS) networks, which may use a mix of electronic and optical links. In particular, we demonstrate that the biswapped connectivity removes an inherent asymmetry of swapped/OTIS networks, as well as the attendant complications in analyses and applications. Finally, we show that biswapped networks are complementary to, and offer advantages over, well-known and widely used interconnection architectures for parallel processing.

New Methodologies for Parallel Architecture

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. Computers, etc.

A Parallel Efficient Architecture for Large Cryptographically Robust n × k (k>n/2) Mappings

We present a scalable, modular, memoryless, and reconfigurable parallel architecture to generate cryptographically robust mappings, which are useful in the construction of stream and block ciphers. It has been theoretically proved that the proposed architecture can be reconfigured to generate a large number of mappings, all of which have high nonlinearity, satisfies Strict Avalanche Criterion (SAC) and is robust against linear and differential cryptanalysis. The architecture can be also used to optimize the resiliency and algebraic degree. The architecture has been found to scale easily to handle large number of input variables, which is an important criterion in realizing nonlinear combiners for stream ciphers using Boolean functions.

FPGA-Based Multiple-Channel Vibration Analyzer for Industrial Applications in Induction Motor Failure Detection

Early detection of failures in equipment is one of the most important concerns to industry. Many techniques have been developed for early failure detection in induction motors. There is the necessity of low-cost instrumentation for online multichannel measurement and analysis of vibration in the frequency domain, and this could be fixed to the machine for continuous monitoring to provide a reliable continuous diagnosis without needing trained staff. Field-programmable gate arrays (FPGAs) are distinguished by being very fast and highly reconfigurable devices, allowing the development of scalable parallel architectures for multichannel analysis without changing the internal hardware. The novelty of this work is the development of a low-cost FPGA based on a multichannel vibration analyzer; this is capable of providing an automatic diagnosis of the motor state carrying out online continuous monitoring. To test the functionality of the proposed vibration analyzer, three experiments on 746-W (1-hp) induction motors were carried out. Such experiments are intended to detect motor failures such as broken bars, unbalance, and looseness. The obtained results show the overall system performance.

Hardware Acceleration of HMMER on FPGAs

We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for biological sequence alignment, based on profile hidden Markov models. We derive a flexible, generic, scalable hardware parallel architecture which can accelerate the core of hmmsearch by nearly two orders of magnitude, without modifying the original algorithm of this software. Our derivation is based on the expression of the algorithm as a set of recurrence equations, and we show in a systematic way how a very efficient parallel version of the algorithm can be found by combining scheduling, projection, partitioning, pipelining and precision analysis. We present the performance of the implementation of this parallel algorithm on a FPGA platform.

Swapped interconnection networks: Topological, performance, and robustness attributes

Interconnection architectures range from complete networks, that have a diameter of D = 1 but are impractical except when the number n of nodes is small, to low-cost, minimally connected ring networks whose diameter D = ⌊ n / 2 ⌋ is unacceptable for large n . In this paper, our focus is on swapped interconnection networks that allow systematic construction of large, scalable, modular, and robust parallel architectures, while maintaining many desirable attributes of the underlying basis network comprising its clusters. A two-level swapped network with n 2 nodes is built of n copies of an n -node basis network using a simple rule for intercluster connectivity (node j in cluster i connected to node i in cluster j ) that ensures its regularity, modularity, packageability, fault tolerance, and algorithmic efficiency. We show how key parameters of a swapped interconnection network are related to the corresponding parameters of its basis network and discuss implications of these results to synthesizing large networks with desirable topological, performance, and robustness attributes. In particular, we prove that a swapped network is Hamiltonian (respectively, Hamiltonian-connected) if its basis network is Hamiltonian (Hamiltonian-connected). These general results supersede a number of published results for specific basis networks and obviate the need for proving Hamiltonicity or Hamiltonian connectivity for many other basis networks of practical interest.

HPF+: High Performance Fortran for advanced scientific and engineering applications

High Performance Fortran (HPF) offers an attractive high-level interface for programming scalable parallel architectures by extending Fortran with directives for specifying data distributions and for indicating parallel execution. The current version of HPF is very well suited for regular codes but lacks important features required for an efficient parallelization of applications based on irregular grids or unstructured meshes. In this paper, we present an optimized version of high performance Fortran, called HPF+, that addresses these requirements. HPF+ provides data distribution features applicable in the context of irregular, dynamically changing data structures and access patterns. Additional mechanisms are introduced to influence the mapping of computations to processors and to reduce the runtime preprocessing and communication overheads of irregular loops. Without sacrificing required functionality, HPF+ adopts a data distribution model based on a one-level mapping of data to processors, reducing the complexity of the language, while alleviating the compiler’s task of producing an efficient parallel program.

VFC: The Vienna Fortran Compiler

High Performance Fortran (HPF) offers an attractive high‐level language interface for programming scalable parallel architectures providing the user with directives for the specification of data distribution and delegating to the compiler the task of generating an explicitly parallel program. Available HPF compilers can handle regular codes quite efficiently, but dramatic performance losses may be encountered for applications which are based on highly irregular, dynamically changing data structures and access patterns. In this paper we introduce the Vienna Fortran Compiler (VFC), a new source‐to‐source parallelization system for HPF+, an optimized version of HPF, which addresses the requirements of irregular applications. In addition to extended data distribution and work distribution mechanisms, HPF+ provides the user with language features for specifying certain information that decisively influence a program’s performance. This comprises data locality assertions, non‐local access specifications and the possibility of reusing runtime‐generated communication schedules of irregular loops. Performance measurements of kernels from advanced applications demonstrate that with a high‐level data parallel language such as HPF+ a performance close to hand‐written message‐passing programs can be achieved even for highly irregular codes.

Evaluation of Cluster-based System for the OLTP Application

In this paper, we have modeled and evaluated a new parallel processing system called Scalable Parallel computer Architecture based on Xbar (SPAX) for commercial applications. SMP systems are widely used as servers for commercial applications; however, they have very limited scalability. SPAX costeffectively overcomes the SMP limitation by providing both scalability and application portability. To investigate whether the new architecture satisfies the requirements of commercial applications, we have built a system model and a workload model. The results of the simulation study show that the I/O subsystem becomes the major bottleneck. We found that SPAX can still meet the I/O requirement of the OLTP workload as it supports flexible I/O subsystem. We also investigated what will be the next most important bottleneck in SPAX and how to remove it. We found that the newly developed system network called Xcent-Net will not be a bottleneck in the I/O data path. We also show the optimal configuration that is to be considered for system tuning.

Incorporating crystallographic texture in deformation process simulations

Computer simulations of metal forming provide an effective means to investigate the relationships between processing deformations and microstructure. Scalable parallel computer architectures enable the direct inclusion of the crystallographic-texture in finite elements used to discretize a workpiece. With evolving texture available, anisotropic properties are computed and used to evaluate a workpiece's response under loading. Two applications are presented here: flat-rolling and sheet-formability testing. The former demonstrates the ability to resolve property gradients arising from heterogeneous deformations through the workpiece thickness. The latter illustrates the ability to compute the impact of texture variations on the formability of metal under different loading states. In addition, the scalability of the formulation is shown with examples.

An Architecture for High Availability Multi-user Systems

This paper describes fault tolerance features of a multiprocessor system called SPAX (Scalable Parallel Architecture based on X-bar network). It aims at a cost-effective reliable multiprocessor system for both scientific and business applications. The system can be composed of up to sixteen clusters. Each cluster consists of eight nodes which can be any combination of processing nodes, input/output nodes and communication nodes. The system is designed to eliminate potential single-points of failures such as loss of a processor, loss of a network, or loss of a disk drive. Xcent-Net, which is a duplicated hierarchical crossbar interconnection network built into the system, supports dual paths to every node with high bandwidth and with low latency. Each node is designed to support multi-level fault tolerance enabling a user to choose the level of fault tolerance with a possible resource or performance penalty. The system has been implemented at ETRI.

DESIGN AND SIMULATION OF THE ON-LINE TRIGGER AND RECONSTRUCTION FARM FOR THE HERA-B EXPERIMENT

The common third level trigger and forth level reconstruction farm for the future HERA-B experiment will have to perform full on-line event reconstruction and calibration for an expected input rate of 2000 events/s. More than a hundred powerful RISC processors connected in a network capable of distributing several hundreds of MB/s with low latency are likely to be necessary for this task. Proper simulation of the real time multi-processor systems is central for an optimal design (hardware and software protocol) of a scalable and flexible parallel data processing architecture. A discrete event, process oriented simulation developed in concurrent μC++ is used as a framework for modelling and evaluating different farm architectures. An object oriented graphic interface to the simulation allows the monitoring of various features and provides an easier way to optimize the system.

A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT SYSTEMS

In this paper we present a VLSI fuzzy processor whose main features are a scalable parallel architecture, and the computation of fuzzy inferences based on the α-level set theory, both of which are important in the field of intensive fuzzy computing, as in fuzzy expert systems. A specific analysis is made in the paper, of techniques for the representation of fuzzy sets, in relation to the amount of area occupied and the forms they can assume. From this analysis a solution is extracted and then used for the processor presented in the paper. The architecture of the processor is chosen after the assessment of possible alternatives by analyzing an appropriate probabilistic model. The processor comprises a set of units which work parallelly and asynschronously to process the various rules. The structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. The performance obtainable is about 310 KFLIPS, with a clock frequency of 60 Mhz, 8 input variables, either crisp or fuzzy, and an 8-bit resolution.

Performance bounds for column-block partitioning of parallel Gaussian elimination and Gauss-Jordan methods

Column-block partitioning is commonly used in the parallelization of Gaussian Elimination (GE) and Gauss-Jordan (GJ) algorithms. It is therefore of interest to know performance bounds of such partitioning on scalable distributed-memory parallel architectures. In this paper, we use a graph-theoretic approach in deriving asymptotic performance lower bounds of column-block partitioning for both GE and GJ. The new contribution is the incorporation of communication cost in the analysis which results in the derivation of sharper lower bounds. We use our scheduling system PYRROS to experimentally compare the actual run time performance with that derived by these lower bounds on the nCUBE-2 hypercube parallel machine.