RX Mode Research Articles

A S-band switchless bi-directional transceiver with a 52% fractional bandwidth in CMOS technology

This paper presents a bi-directional switchless wideband transceiver front-end for S-band multi-functional digital array system. In an S-band digital array system, a silicon-based RF front-end module requires a high integration level, compact size, large bandwidth, and low power consumption features. A bi-directional switchless transceiver could provide a compact solution. However, the shared RF matching network in such a transceiver is crucial due to its influence on Rx sensitivity, Tx output power, TRx isolation, and bandwidth. This work proposes a compact π matching network for simultaneous broadband Rx noise matching, Tx power matching, and TRx isolation. Also, a double quadrature down-conversion architecture is proposed to improve image signal rejection in the whole S-band. Therefore, false detection in the S-band digital array can be avoided. Fabricated in a 0.18μm CMOS technology, this S-band transceiver occupies a silicon area of 3.2 × 2 mm2. In the Rx mode, the measured gain is 20.7–28 dB in 2–4 GHz at 25 °C. The RX noise figure is 9.5–11.5 dB, and the input 1-dB compression point is -11 dBm. In the Tx mode, the gain is 16.5–19.6 dB in 2–4 GHz at 25 °C, and Psat is 10.2 dBm. The RX bandwidth is 2–3.4 GHz, while that of Tx is 2–4 GHz. The corresponding fractional bandwidth is 52% and 67%, respectively. Furthermore, this transceiver shows an image rejection ratio of 28.9–41.4 dB suppression at the operation frequency band.

Design and Analysis of Complementary Metal–Oxide–Semiconductor Single-Pole Double-Throw Switches for 28 GHz 5G New Radio

We propose a single-pole double-throw (SPDT) switch with low insertion loss (IL), high isolation, and high linearity for a 28 GHz 5G new radio. The transmit (TX) path is a π-network consisting of a parallel dynamic-threshold metal–oxide–semiconductor (DTMOS) transistor, M1, with large body-floating resistance, RB (DTMOS-R M1), a series one-eighth-wavelength (λ/8) transmission line (TL), and a parallel capacitance, Cant. The series λ/8-TL in conjunction with the parallel Cant and transistors’ capacitance constitute an equivalent λ/4-TL with a characteristic impedance of 50 Ω. This leads to low IL in the TX mode and decent isolation in the receive (RX) mode. The RX path is an L-network constituting a series impedance (of parallel inductance L1 and DTMOS-R M2) and a parallel DTMOS-R M3. This leads to a decent IL in the RX mode and isolation in the TX mode. The first SPDT switch (SPDT SW1) is designed and implemented in a 90 nm complementary metal–oxide–semiconductor (CMOS) with a top metal thickness (TMT) of 3.4 μm. A comparative SPDT switch (SPDT SW2) in a 0.18 μm CMOS with a thinner TMT of 2.34 μm is also designed and implemented. In the TX mode, SPDT SW1 achieves a measured IL of 0.67 dB at 28 GHz and 0.58–1 dB for 17–34.9 GHz and a measured isolation of 44.3 dB at 28 GHz and 25.6–62.3 dB for 17–34.9 GHz, one of the best IL and isolation results ever reported for millimeter-wave CMOS SPDT switches. The measured input 1 dB compression point (P1dB) is 28.5 dBm at 28 GHz. Moreover, in the RX mode, SPDT SW1 attains a measured IL of 1.9 dB at 28 GHz and 1.83–2.1 dB for 25–38.3 GHz and an isolation of 25 dB at 28 GHz and 24.5–27 dB for 25–38.3 GHz. The measured P1dB is 24 dBm at 28 GHz.

A novel Q‐band asymmetric T/R switch in GaAs pHEMT using second‐order band‐stop filter for wideband RX‐mode isolation

AbstractTo improve the RX‐mode isolation of asymmetric T/R switches, a new circuit topology is proposed. The proposed asymmetric T/R switch topology features a second‐order band‐stop filter in its TX path, which extends the bandwidth of isolation in the RX mode. Based on the proposed topology, a Q‐band asymmetric T/R switch is designed and implemented in a 0.15‐µm GaAs pHEMT technology. Measured isolation in the RX mode is greater than 18.4 dB from 31.7 to 46.3 GHz, corresponding to a 1.46:1 bandwidth.

A Multimode 28 GHz CMOS Fully Differential Beamforming IC for Phased Array Transceivers

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm2, including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.

A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station

This article demonstrates a 39-GHz CMOS phased-array beamformer aiming for power-efficient and area-efficient fifth-generation (5G) dual-polarized multiple-in–multiple-out (DP-MIMO) applications. To address the digital pre-distortion (DPD) implementation issue in the massive beamformer elements with Doherty technique integrated, an inter-element mismatch compensation technique is introduced for improving the shared-lookup table (LUT) DPD performance over the process, voltage and temperature (PVT) variations. A bidirectional Doherty power amplifier (PA)-LNA is proposed to enhance the power back-off (PBO) efficiency regarding the high peak-to-average power ratio (PAPR) 5G signals, meanwhile cost down the system by the unbalanced neutralized bidirectional operation. The proposed phased-array beamformer chip is fabricated in 65-nm CMOS technology and packaged in a wafer-level chip-scale package (WLCSP). Each element occupies only a 0.82-mm2 chip area, including the on-chip low-dropout regulator (LDO). The measured stand-alone Doherty PA-LNA achieves 18.9-dBm saturated output power with 17.8% power-added efficiency (PAE) at 6-dB PBO in PA mode and obtains a 4.8-dB noise figure (NF) at 40 GHz in LNA mode. By utilizing the proposed mismatch compensation, the measured 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiple access (OFDMA)-mode error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) with the shared-LUT DPD are improved from −22.4 to −25.0 dB and from −28.7 to −32.1 dBc, respectively. The 64-element module achieves a 55.2-dBm saturated effective isotropic radiated power (EIRP) and supports 21-Gb/s single-carrier (SC) mode data streaming. The measured 64-element transmitter (TX) EVM is −25.2 dB at 43.2 dBm with 3.5-GSymbol/s baud rate in 64 QAM, and the corresponding 64-to-4 elements TX-to-receiver (RX) EVM is −22.5 dB. The consumed power for each element is 402 mW at saturation output point in TX mode and 87 mW in RX mode.

An 11-15GHz multifunctional MMIC with 1.7° RMS phase error, 26.5dBm P<sub>sat</sub> and >30% PAE for T/R module

This paper presents an 11-15GHz MMIC multifunction chip (MFC) with phase and amplitude control. The chip is based on the common-leg structure and comprises a phase shifter (PS), attenuator (ATT), T/R switch, gain compensation amplifiers (AMPs), driver stage AMPs and parallel control circuits. In the 11-15GHz bandwidth, measurements show that the gain and saturation power (Psat) are higher than 21.5dB and 26.5dBm, while the efficiency is more than 30% in TX mode. In RX mode, the small signal gain is more than 10.2dB, the NF is less than 9.8dB, and output 1dB power (OP1dB) is more than 8.5dBm. The measured minimum RMS phase and amplitude errors are 1.7° and 0.45dB, respectively.

Area-Efficient 28-GHz Four-Element Phased-Array Transceiver Front-End Achieving 25.2% Tx Efficiency at 15.68-dBm Output Power

An area-efficient 28-GHz four-element phased-array transceiver front-end (TRx FE) is proposed in this article. Transmitter/receiver (T/R) switch, phase shifter (PS), and power combining/splitting network all use customized coupler-based structures to replace area-consuming quarter-wavelength ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4) transmission line (T-line) structures. In Tx mode, a three-stage power amplifier (PA) is designed by cascading a class-AB predriver amplifier, a deep class-AB driver amplifier, and a class-A output amplifier for high output power. In Rx mode, a two-stage low noise amplifier (LNA) is designed with a 3-bit resistive adjusting load for high dynamic range of input power. A coupler is adopted in the variable gain amplifier (VGA) to achieve constant phase during gain adjustment. The proposed TRx FE is fabricated in a 40-nm CMOS process. Measurement results show that output 1-dB compression point (OP1dB) of 14.99 dBm and saturated output power (OPsat) of 15.68 dBm with 25.2% power efficiency are achieved in each Tx element. In each Rx element, noise figure (NF) of 4.54 dB, input 1-dB compression point (IP1dB) of −10.15 dBm, and maximum gain of 26.3 dB with 56.1-mW power consumption are realized. The gain range of Rx/Tx mode is 9.9–26.3 dB/24.2–44.6 dB with a resolution of 0.3 dB and phase variation less than 2° at 28 GHz. Thanks to the area-efficient coupler-based structures, the phased-array TRx FE occupies an area of 0.42 mm2 for each element and 0.084 mm2 for total area of combiner/splitter, achieving high area efficiency for Ka-band phased-array TRx FEs.

Low-cost high-speed rapidly reconfigurable integrated half-duplex optical transceiver front-end.

We present and demonstrate an integrated approach to make low-cost high-speed half-duplex optical transceiver with rapid reconfigurability. A single Distributed-Feedback (DFB) diode is employed as the unified E/O-O/E device, which is dynamically biased as laser or photodetector in transmitter or receiver mode. The bias for the DFB and the transmit/receive (T/R) signal path are provided by a custom-designed reconfigurable CMOS chip, which contains the biasing circuitry, a high-speed T/R switch and a burst-mode transimpedance amplifier (BM-TIA). The transceiver front-end operates up to 5 Gb/s for both transmitter (Tx) and receiver (Rx) mode experimentally, while its reconfiguration time is less than 131 ns. This integrated approach not only halves the transceiver optics to facilitate low cost, but also enables high-speed signal transmission as well as rapid reconfiguration, which will be critical for the fiber-to-everything paradigm shift in the near future.

High-Efficiency 28-/39-GHz Hybrid Transceiver Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile Applications

This letter presents the first demonstration of 5G millimeter-wave hybrid front-ends (FEs) for a phased-array transceiver in order to show efficient transmitter performance with low cost and compact area. The configuration of the proposed hybrid FEs is CMOS-based FEs combined with compact GaAs HEMT-based power-cell array to obtain all the benefits of silicon and III-V technology. The architecture and design method of a millimeter-wave transmitter (TX)/receiver (RX) combiner for antenna-port sharing suitable for the proposed hybrid structure is newly introduced. A developed 29-GHz transceiver FE achieves a linear output power of 14.9 dBm with PAE of 28.5% at SC-FDMA 64QAM 100-MHz EVM of −25 dB in TX mode and noise figure (NF) of 5.5 dB in RX mode. Moreover, a developed 38-GHz transceiver FE achieves a linear output power of 12.8 dBm with PAE of 25.2% at SC-FDMA 64QAM 100-MHz EVM of −25 dB in TX mode and NF of 5.5 dB in RX mode.

An Ultra-Compact Bidirectional Ka-Band Front-End Module With 3.8-dB NF and 13.5-dBm OP1 dB

This letter presents an ultra-compact bi-directional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band front-end module (FEM) in 65-nm CMOS technology. In this design, the receiver (RX) path is stacked into the transmitter (TX) path by using a magnetic self-canceling technique, improving area efficiency greatly with negligible performance penalty. Furthermore, a three-inductor coupled resonator is elaborately designed to realize the functions of the balun and input–output matching network (MN) of the RX/TX simultaneously. The measurement results demonstrate that the proposed FEM achieves 18.2-dB peak gain with a 3.8-dB minimum noise figure (NF) in RX mode, and 26-dB peak gain with 13.5-dBm 1-dB compression output power (OP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{1\,{\mathrm {dB}}}$ </tex-math></inline-formula> ) in TX mode. The core size of this proposed design is only 0.06 mm2 which is only 20%–50% of the size occupied in prior works.

Design of a K-Band High-Linearity Asymmetric SPDT CMOS Switch Using a Stacked Transistor

This study presents a high-linearity K - band single-pole double-throw (SPDT) switch with asymmetric topology in a 65-nm CMOS process for 5G applications. To simultaneously obtain high power-handling capability and high isolation in the Tx and Rx modes, respectively, we propose an SPDT switch using asymmetric topology and the stacked-transistor technique. In both the Tx/Rx modes, the proposed SPDT switch operates with an insertion loss of less than 2.1 dB and isolation better than 22.5 dB in the frequency range 20–25 GHz. At 22 GHz, the measurement results of the input 1-dB compression point (IP1 dB) are 32.5 and 4.7 dBm in Tx and Rx modes, respectively. The chip core size of the proposed SPDT switch is 0.03 mm2.

A CMOS 4‐Element Ku‐Band Phased‐Array Transceiver

This paper presents a Ku-Band fully differential 4-element phased-array transceiver using a standard 180-nm CMOS process. Each transceiver is integrated with a 5-bit phase shifter and 4-bit attenuator for high-resolution radiation manipulation. The front-end system adopts time-division mode, and hence two low-loss T/R switches are included in each channel. At room temperature, the measured root-mean-square (RMS) phase error is less than 5.5°. Furthermore, the temperature influence on passive switched phase shifters is analyzed. Meanwhile, an extra phase-shifting cell is developed to calibrate phase error varying with the operating temperatures. With the calibration, the RMS phase error is reduced by 7° at −45 ℃, and 5.4° at 85 ℃. The RMS amplitude error is less than 0.92 dB at 15−18 GHz. In the RX mode, the tested gain is 9.6±1.1 dB at 16.5 GHz with a noise figure of 10.9 dB, and the input P1dB is −15 dBm, while the single-channel's gain and output P1dB in the TX mode are 11.3±0.4 dB and 9.4 dBm at 16.1 GHz, respectively. The whole chip occupies an area of 5×4.2 mm2 and the measured isolation between each two adjacent channels is lower than −23.1 dB.

Advances in Ku-Band GaN Single Chip Front End for Space SARs: From System Specifications to Technology Selection

In this paper, a single-chip front-end (SCFE) operating in Ku-band (12–17 GHz) is presented. It is designed exploiting a GaN on SiC technology featured by 150 nm gate length provided by UMS foundry. This MMIC integrates high power and low noise amplification functions enabled by a single-pole double-throw (SPDT) switch, occupying a total area of 20 mm2. The transmitting chain (Tx) presents a 39 dBm output power, a power added efficiency (PAE) higher than 30% and a 22 dB power gain. The receive path (Rx) offers a low noise figure (NF) lower than 2.8 dB with 25 dB of linear gain. The Rx port output power leakage is limited on chip to be below 15 dBm even at high compression levels. Finally, a complete characterization of the SCFE in the Rx and Tx modes is presented, also showing the measurement of the recovery time in the presence of large-signal interferences.

A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation

This article introduces a four-element 300-GHz-band bi-directional phased-array transceiver (TRX). The TRX utilizes the same antenna, signal path, and local oscillator (LO) circuitry to operate either in transmitter (TX) mode or receiver (RX) mode. The TX mode adopts the outphasing technique to increase the average output power for higher order modulation schemes by utilizing the two mixers that are connected directly to the antenna in a mixer-last fashion. The two signal paths also enable the canceling of the LO feed-through (LOFT). The RX mode also benefits from the LOFT cancellation technique to suppress the LO emission, which is a common issue of the mixer-first RXs. The RX has a separate Hartley operation mode to reject the image signal coming from the TX. The TRX chip was implemented using CMOS 65-nm process, and a four-element phased array was implemented by stacking liquid crystal polymer (LCP) flexible printed circuit boards (PCBs). The stacked structure provides the required narrow antenna pitch at the 300-GHz band. The measured beam angle range is from −18° to 18°. The single-element power consumption is 750 mW for both TX mode and RX mode.

A high‐precision and fast off‐line beamforming pattern estimation technique for active phased array antenna application

A detailed modeling method including all states of each active devices is proposed in this work, aiming to achieve high-precision and fast off-line estimation of beamforming pattern. Experimental verification of hundreds of radiating patterns shows that the beam steering angle accuracy is able to obtain 0.2% (Tx mode) and 0.19% (Rx mode) beam width in average, respectively; and the beam width accuracy is 0.2% (Tx mode) and 0.39% (Rx mode) in average, respectively. Also, SLL accuracy can reach 0.01 dB (Tx mode) and 0.1 dB (Rx mode), respectively. By adopting this technology, the optimal beam controlling codes of large active phased array antenna (APAA) could be quickly derived. Furthermore, measurement and online compensation works of enormous quantities of beams could be greatly simplified.

Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS

This article presents novel methodologies and practical design considerations for a <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain <inline-formula> <tex-math notation="LaTeX">$G_{p}$ </tex-math></inline-formula> of 33.6/35.7 dB, a saturated output power <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ sat}}$ </tex-math></inline-formula> of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3&#x0025;, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power (<inline-formula> <tex-math notation="LaTeX">${P_{out}}_{avg}$ </tex-math></inline-formula>)/PAE of 4.9 dBm/2&#x0025; is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of &#x2212;24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB <inline-formula> <tex-math notation="LaTeX">$G_{p}$ </tex-math></inline-formula>, a &#x2212;24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm², respectively.

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

This article introduces a wirelessly powered phased-array transceiver for fifth-generation (5G) relay systems. To realize the battery-less relay operation, 24-GHz wireless power transfer (WPT) is employed. This relay transceiver consists of the proposed vector-summing backscatter for Transmitter (Tx) and a passive phase-shifting self-heterodyne Receiver (Rx) with a rectifier for Rx and WPT. The receiver generates dc power from the 24-GHz WPT signal, which is also used as a local oscillator (LO) signal to down-convert the 28-GHz 5G modulated data to a 4-GHz IF. The vector-summing backscatter up-converts the 4-GHz IF signal to 28-GHz using a 24-GHz LO signal while working as a 360° phase shifter with a 7-bit resolution. Both transmitter and receiver operate only using the generated power from the 24-GHz WPT. The chip area of the eight-path transceiver is 1.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the transceiver is mounted on a 32-element phased-array antenna board. This module generates 3.1-mW dc power from 6.7-mW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> received power density at 24 GHz. The transmitter achieves a −2.2-dBm measured saturated equivalent isotropically radiated power (EIRP) and supports a −30° to +30° beam range. The measured error vector magnitude (EVM) values are −27.5 dB for Tx mode and −31.3 dB for Rx mode with a 400-MHz 64-QAM orthogonal frequency division multiple access (OFDMA)-mode signal (5G new radio (NR), MCS 19). The power consumption for each path is 0.03 mW in both Tx and Rx modes.

A Novel Energy-Conscious Access Point (eAP) System With Cross-Layer Design in Wi-Fi Networks for Reliable IoT Services

This paper proposes a novel energy-conscious access point (<i>e</i>AP) system with cross-layer design to increase the energy efficiency of IoT devices in IEEE 802.11 Wi-Fi networks for reliable IoT services. The proposed <i>e</i>AP system controls the energy resources of IoT devices to extend the lifetime of the IoT device. For this purpose, we develop a new <i>e</i>AP system that considers a cross-layer design with a prompt TCP ACK transmit function, a caching-and-retransmit IoT data function, and a multiple IoT data aggregate function to improve the energy efficiency of the IoT device. In addition, the proposed <i>e</i>AP system has a device energy management module that precisely controls operating parameters, such as the transmission period of IoT packets, the delivery of traffic indication message (DTIM) value of IoT devices, and the transmitting power of IoT devices. These features extend the lifetime of the battery-powered IoT devices while satisfying service requirements for reliable IoT services. The long listening time of TCP ACK messages in receive mode (Rx) results in the high energy consumption of IoT devices due to the large round trip time. The proposed <i>e</i>AP system reduces the reception time of TCP ACK messages in the IoT device, using the prompt TCP ACK transmit function in the <i>e</i>AP. This reduces the long Rx mode time for TCP ACK reception, and increases the short sleep mode time, which results in increase of the energy efficiency of the IoT device. In the energy-saving analyses, we formulate an energy consumption model for the IoT device, and determine the energy-saving gain when the IoT device uses the <i>e</i>AP system model, compared to a legacy AP system model. Our performance evaluation results verify that the proposed <i>e</i>AP system achieves a maximum improvement in energy efficiency of approximately 88%, and 8.4 times improvement in the expected lifetime of the IoT device, compared to the legacy AP system model.

A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse

This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> 1dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is 1.24×/1.51×/1.72× at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent -27.1dB EVM, -31.31dBc ACLR, 14.6dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves < -60 dBm LO leakage over the operating frequency range.

A 90-GHz Asymmetrical Single-Pole Double-Throw Switch With &gt;19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .