RLGC Model Research Articles

Signal Integrity Analysis of Through-Silicon Via (TSV) With a Silicon Dioxide Well to Reduce Leakage Current for High-Bandwidth Memory Interface

In this paper, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate’s effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented, and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7 % and 4.7 % at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1 % at 8 Gb/s, verifying the low-power structure.

Design and modeling of novel TSV for ternary logic applications

In this paper presents the TSVs are made of conducting material which is implanted in silicon substrate with dielectric liner coated around the metal line. The study of ternary logic signal propagation in through silicon vias is more important since the ternary signals have small noise margins. Moreover, due to the crosstalk noise the fault switching probability is increases in logic circuits. In this work, a novel TSV structure named as metal semiconductor TSVs for the propagation of ternary logic signals has been proposed. Using the proposed model, the probability of occurring the fault tolerance has been reduced and also the performance is enhanced. The proposed model is developed with an analytical RLGC model where the parasitic values are extracted from electromagnetic field solvers. The simulation results of proposed structures are compared with conventional metal–insulator-semiconductor TSVs to show improvements.

Impact of Polymer Liners on Crosstalk Induced Delay of Different TSV Shapes

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material, SiO2, is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes, considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T-type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.

Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via

At high frequency, a magnetic field induced eddy current primarily dominates the performance of a through silicon via (TSV) based 3D interconnects. In this regard, this paper considered a copper (Cu) based cylindrical-shaped TSV by considering the impact of eddy current on the silicon substrate, depletion layer, and neighboring TSVs at a high frequency. Further, an equivalent novel resistance-inductance-conductance-capacitance (RLGC) circuit model is presented in order to investigate the crosstalk induced delay under the consideration of eddy current. Therefore, a closed-form analytical expression of the eddy resistance is derived using the Quasi-magnetostatic field's theory. A unique eddy based pi-type distributed RLGC model is used to analyze the in-phase and out-of-phase crosstalk delay using three coupled driver-via-load (DVL) at 32 nm technology. Using industry-standard HSPICE circuit simulations, the crosstalk induced delay is obtained for 20 to 500 GHz operating frequencies at different via heights ranging from 30 to 120 μm. It has been observed that the overall rate of change in out-phase and in-phase crosstalk-induced delay with considering eddy effect are 21.8% and 14.5%, respectively for via height of 120 μm.

Slow-Wave Microstrip Line Model for PCB and Metallic-Nanowire-Filled-Membrane Technologies

An electrical model composed of lumped elements is proposed for slow-wave microstrip lines that use grounded blind vias/nanowires to achieve the slow-wave effect. The main difference of this model, from the traditional RLGC model for transmission lines, is the modeling of the blind vias/nanowires that consider a mutual inductive coupling considered between sections of the model. Two transmission lines on two technologies are analyzed: printed circuit board (PCB) and metallic nanowire-filled membrane (MnM) substrate. The calculi for each component of the model are detailed. Electrical simulations are done, and a comparison between the measured and simulated data is shown. It is shown that the electrical model can predict the transmission lines' behavior, especially the dispersion on the results that happen in frequency.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

In this paper, a novel through-silicon via (TSV) structure, named partial coaxial TSV (PC-TSV), is proposed to suppress TSV-induced substrate noise. In this structure, the via is surrounded by a benzocyclobutene (BCB) layer, and a grounded metal ring placed at one end. The BCB layer can effectively reduce the leakage of the signal to the substrate, and the metal ring provides a low impedance path for the substrate noise. An equivalent RLGC model of this structure is also established, and it is verified by simulated result from CST. Then, the performance of PC-TSV is compared with that of the traditional TSV, TSV with p+ layer, and TSV with p+ guard ring. Analysis results in frequency domain indicate PC-TSV has a larger $\vert \text{S}_{21}\vert $ and less near-end crosstalk than other three structures. Additionally, analysis results in time domain show that the substrate voltage noise of this structure is obviously reduced compared with the TSV with p+ layer and TSV with p+ guard ring. Also, a feasible process flow for this structure is given and it is simpler than that for traditional coaxial TSV.

High-Frequency Electrical Characterization of a New Coaxial Silicone Rubber Socket for High-Bandwidth and High-Density Package Test

This paper, for the first time, proposes and verifies a new coaxial silicone rubber socket for high-bandwidth and high-density package test using a fabricated sample. In addition, this paper also characterizes and verifies the coaxial silicone rubber socket. Because of the proposed coaxial socket’s novel coaxial structure, the proposed socket successfully achieves the electrical performance improvement. For verification, we compare the proposed socket and the previous noncoaxial socket in time domain. The proposed socket has greater eye height and eye width in the measured eye diagram than those of the noncoaxial socket. Moreover, the slope in the eye diagram is also improved in the case of the proposed socket. Therefore, the measured eye diagram for the coaxial socket shows the improvement in electrical performances. This paper also characterizes the equivalent RLGC model for the coaxial silicone rubber socket. In order to verify the RLGC model, we compare the insertion losses and eye diagrams from measurement, 3-D electromagnetic simulation, and the proposed RLGC model, respectively. Their insertion losses are comparable up to 20 GHz. Furthermore, the obtained eye diagrams are almost identical at the data rate of 9.6 Gb/s. In conclusion, this paper successfully proposes, verifies, and characterizes a new coaxial silicone rubber socket for the first time.

Parameter extraction method for the twisted pair cable with rectangular connectors.

Cables play an important role in transmitting energy and information. In this article, in order to obtain the S-parameters of the special twisted pair cable with rectangular connectors, a de-embedding method of the transmission matrix is proposed to deal with the two adapters ends of the cable. According to the frequency-dependent RLGC(f) model, the cable characteristics are extracted in the frequency range of 10 MHz to 200 MHz through conventional and modified methods respectively. The frequency-domain analysis shows that the inherent capacity of modified method can decrease the errors especially due to the discontinuities of hyperbolic functions. This research supplies an advantageous modelling approach for the cable to improve its robustness against disturbances in the S-parameters measurement that cannot be decreased with the calibration procedure.

Application of RLGC modeling in probing the electrical properties of monolayer graphene at microwave frequencies

The S-parameters of the microstrip line loaded with graphene on glass and graphene on quartz as a superstrate are measured from 10 MHz to 26.5 GHz. These parameters have shown only a little difference compared to glass or quartz loaded microstrip line. Then, de-embedded S-parameters of superstrate loaded microstrip line are modeled as the transmission line (RLGC) parameters and these parameters are obtained with frequency. Their comparison with unloaded microstrip line shows large changes in R and G whereas, in L and C parameters, no significant changes have been noticed with superstrates. In these parameters, larger percentage changes for graphene on glass have showed a poor contact between two than graphene and quartz. Changes in R and G parameters confirmed that graphene has modified the surface resistance and effective relative permittivity on loading the microstrip line.

RLGC(f) modeling of a busbar distribution system via measured S-parameters at CENELEC and FCC bands

This paper addresses the extraction of accurate frequency-dependent per-unit-length RLGC parameters for busbar distribution systems using measured S-parameters for the CENELEC and FCC bands. A busbar is a distribution system element (three phase, low voltage) with a modular structure that carries electrical energy in buildings. The S-parameters of a busbar distribution system at different current levels (630 A, 1250 A, 2000 A) are measured with a vector network analyzer and then analyzed for three different two-port connections (L1-N, L2-N, L3-N). A frequency- dependent RLGC(f) model is used to characterize the busbar as a transmission line using a derivative-free optimization algorithm. A time-domain causality check is also conducted. Estimated RLGC parameters are presented along with characteristic impedance and propagation constant. Good agreement has been achieved between measured and estimated S-parameters.

S-parameters-based causal RLGC(f) model of busbar distribution systems for broadband power line communication

Busbar power distribution systems are used extensively to carry energy asa noteworthy part of the low-voltage grid. In order to investigate the possibilities of a busbar system for low-voltage, broadband, power-line communication, the system is analyzed asa transmission line. For this purpose, S-parameter measurements at 1–50MHz were conducted to represent the busbar using the frequency-dependent RLGC(f) model. The model’s parameters were optimized with a two-step procedure to determine the optimal ranges of the parameters. To prove the causality of the busbar model, both time-domain and frequency-domain verifications were conducted. This points out that the model is causal and provides good agreement between simulated and measured S-parameters. The transfer characteristics of the busbar distribution network were taken out with the frequency-domain modeling approach by using the chain-scattering matrix method. The channel’s performance under different network configurations, e.g., length, branch, and load, was investigated to provide a beneficial contribution for communication system designers.

Applying the Retarded Solutions of Electromagnetic Fields to Transmission Line RLGC Modeling

The RLGC model, and its variations, is one of the most common techniques to simulate Transmission Lines. The RLGC model uses circuit network elements consisting of Resistance R, Inductance L, Conductance G and Capacitance C (per unit length) to represent a small segment of the Transmission Line, and then cascades multiple segments to simulate the Transmission Line of arbitrary length. Typically the parameters in RLGC model are extracted from the propagation constant and characteristic impedance of the transmission line, which are found using numerical simulation methods. These resulting RLGC parameters for multi-GHz signaling are usually frequency-dependent. This paper introduces an analytical approach to extract RLGC parameters to simulate transmission line, which results in a different model, the RLGC(p) model.

Analysis and Design of Helix-on-Pads for Miniaturized Mobile Applications

In this paper, a quantitative analysis to obtain the equivalent circuit parameters of helix-on-pads (HoPs) is presented. To simplify the analysis, the HoP, which is a kind of helical wires vertically mounted on a dielectric substrate, is subdivided into two parts using the split-up method based on field distribution. The analysis derives RLGC formulas of the HoPs for various dimensions and number of loops. To verify the accuracy of the derived RLGC model, electromagnetic (EM) simulations for various HoPs cases are also performed. The EM-simulated results show a good agreement with the calculated results. To experimentally demonstrate the analysis and usefulness of the HoP, two HoPs are designed and fabricated for W-CDMA dual-band (Band-2 and Band-5) handset power amplifier (PA) applications. Measured RF performances of the standalone HoPs and composite PA show good agreements with the calculated results, thus validating the usefulness of the analysis and design.

High-Frequency Temperature-Dependent Through-Silicon-Via (TSV) Model and High-Speed Channel Performance for 3-D ICs

Noise coupling through the substrate or silicon interposer among adjacent TSVs has a significant impact on the signal integrity of the TSVs. Since resistance and capacitance are dependent on temperature, more accurate electrical models for TSVs should incorporate the temperature dependency of the material. This paper presents high-frequency temperature-dependent RLGC models for two neighboring TSVs and for two neighboring TSV channels. After validating the models against data measured from a fabricated test vehicle, the paper investigates the impact of temperature on noise coupling between TSVs and TSV channels.

Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays

In this paper, a novel library-based macro-modeling technique is developed to extract equivalent RLGC model which is spice compatible for TSV arrays of any size N M. The built model accounts for Th...

Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays

In this paper, a novel library-based macro-modeling technique is developed to extract equivalent RLGC model which is spice compatible for TSV arrays of any size N×M. The built model accounts for Through Silicon Via (TSV) parasitic dependence on the array structural parameters and the frequency dependent properties of the silicon substrate. The developed macro-model constructs an equivalent parasitic matrix that could be used by circuit simulators to estimate the maximum signal frequency as well as noise in the TSV array. The key idea of the macro-model is to partition any given TSV arrays into smaller and fixed-size arrays. Smaller arrays are characterized and their parasitic are stored in the library. Using a divide and conquer technique, the final solution of the TSV array is produced. A detailed comparison of the proposed macro-modeling technique against the parasitic extracted by microwave simulation, for different structures with different sizes, shows a maximum error of 10% and an average error of 5%. Furthermore, the performance of library based macro-modeling is order of magnitude faster than the microwave simulation.

Modeling Coupled Transmission Lines Considering Current-Distribution Dependent Inductance on PCB

This letter presents the development and parameter extraction of an RLGC model for coupled lines on printed circuit board (PCB) technology. The model incorporates the representation of the common and differential signal propagation modes. Furthermore, the impact of the current distribution on the series inductance is taken into account, achieving excellent model-experiment correlation of $S$ -parameters up to 20 GHz and for a rise time as small as 50 ps.

An accurate RLGC circuit model for dual tapered TSV structure

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Full RLGC model extraction of Through Silicon Via (TSV) with charge distribution effects

The analytical model based on Poisson–Boltzmann equation in a cylindrical coordinate system is developed for simulating the electrical parameters of the three-dimensional Through Silicon Via (TSV) interconnection. Considering the effects of bias voltage, the accurate charge distribution and the high-frequency capacitance in the depletion layer of the semiconductor is obtained. Moreover, the resistance and inductance parameters of TSV are extracted by using the partial element equivalent circuit method. Finally, the full resistance–inductance–capacitance–conductance electrical model of TSV interconnection is presented first time with the semiconductor behaviour, and the transmission characteristics of signal-ground TSV structure are studied.