Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via

Abstract

At high frequency, a magnetic field induced eddy current primarily dominates the performance of a through silicon via (TSV) based 3D interconnects. In this regard, this paper considered a copper (Cu) based cylindrical-shaped TSV by considering the impact of eddy current on the silicon substrate, depletion layer, and neighboring TSVs at a high frequency. Further, an equivalent novel resistance-inductance-conductance-capacitance (RLGC) circuit model is presented in order to investigate the crosstalk induced delay under the consideration of eddy current. Therefore, a closed-form analytical expression of the eddy resistance is derived using the Quasi-magnetostatic field's theory. A unique eddy based pi-type distributed RLGC model is used to analyze the in-phase and out-of-phase crosstalk delay using three coupled driver-via-load (DVL) at 32 nm technology. Using industry-standard HSPICE circuit simulations, the crosstalk induced delay is obtained for 20 to 500 GHz operating frequencies at different via heights ranging from 30 to 120 μm. It has been observed that the overall rate of change in out-phase and in-phase crosstalk-induced delay with considering eddy effect are 21.8% and 14.5%, respectively for via height of 120 μm.