Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays

Abstract

In this paper, a novel library-based macro-modeling technique is developed to extract equivalent RLGC model which is spice compatible for TSV arrays of any size N×M. The built model accounts for Through Silicon Via (TSV) parasitic dependence on the array structural parameters and the frequency dependent properties of the silicon substrate. The developed macro-model constructs an equivalent parasitic matrix that could be used by circuit simulators to estimate the maximum signal frequency as well as noise in the TSV array. The key idea of the macro-model is to partition any given TSV arrays into smaller and fixed-size arrays. Smaller arrays are characterized and their parasitic are stored in the library. Using a divide and conquer technique, the final solution of the TSV array is produced. A detailed comparison of the proposed macro-modeling technique against the parasitic extracted by microwave simulation, for different structures with different sizes, shows a maximum error of 10% and an average error of 5%. Furthermore, the performance of library based macro-modeling is order of magnitude faster than the microwave simulation.