Design and modeling of novel TSV for ternary logic applications

Abstract

In this paper presents the TSVs are made of conducting material which is implanted in silicon substrate with dielectric liner coated around the metal line. The study of ternary logic signal propagation in through silicon vias is more important since the ternary signals have small noise margins. Moreover, due to the crosstalk noise the fault switching probability is increases in logic circuits. In this work, a novel TSV structure named as metal semiconductor TSVs for the propagation of ternary logic signals has been proposed. Using the proposed model, the probability of occurring the fault tolerance has been reduced and also the performance is enhanced. The proposed model is developed with an analytical RLGC model where the parasitic values are extracted from electromagnetic field solvers. The simulation results of proposed structures are compared with conventional metal–insulator-semiconductor TSVs to show improvements.