RISC Instruction Research Articles

The Arm Morello Evaluation Platform—Validating CHERI-Based Security in a High-Performance System

Memory safety issues are a persistent source of security vulnerabilities, with conventional architectures and the C/C++ codebase chronically prone to exploitable errors. The Capability Hardware Enhanced RISC Instructions (CHERI) research project has explored a novel architectural approach to ameliorate such issues using unforgeable hardware capabilities to implement pointers. Morello is an Arm experimental platform for evaluation of CHERI in the Arm architecture context to explore its potential for mass-market adoption. This article describes the Morello Evaluation Platform, covering the motivation and functionality of the Morello architectural hardware extensions; their potential for fine-grained memory safety and software compartmentalization; formally proven security properties; impact on the microarchitecture of the high-performance, out-of-order multiprocessor Arm Morello processor; and the software-enablement program by Arm, the University of Cambridge, and Linaro. Together, this allows a wide range of researchers in both industry and academia to explore and assess the Morello platform.

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture

Capability Hardware Enhanced RISC Instructions (CHERI) supplement the conventional memory management unit (MMU) with instruction-set architecture (ISA) extensions that implement a capability system model in the address space. CHERI can also underpin a hardware-software object-capability model for scalable application compartmentalization that can mitigate broader classes of attack. This article describes ISA additions to CHERI that support fast protection-domain switching, not only in terms of low cycle count, but also efficient memory sharing with mutual distrust. The authors propose ISA support for sealed capabilities, hardware-assisted checking during protection-domain switching, a lightweight capability flow-control model, and fast register clearing, while retaining the flexibility of a software-defined protection-domain transition model. They validate this approach through a full-system experimental design, including ISA extensions, a field-programmable gate array prototype (implemented in Bluespec SystemVerilog), and a software stack including an OS (based on FreeBSD), compiler (based on LLVM), software compartmentalization model, and open-source applications.

Side-channel leakage models for RISC instruction set architectures from empirical data

Side-channel attacks are currently among the most serious threats for embedded systems. Popular countermeasures to mitigate the impact of such attacks are masking schemes, where secret intermediate values are split in two or more values by virtue of secret sharing. In case of unwanted correlations between different registers inside the CPU, the shared secret may leak through a side-channel. This problem is particularly evident on low cost embedded systems, such as nodes for the Internet of Things (IoT), where cryptographic algorithms are often implemented in pure software on a reduced instruction set computer. On such an architecture, all data manipulation operations are carried out on the contents of the CPU’s register file. This means that all intermediate values of the cryptographic algorithm pass through the register file. Towards avoiding unwanted leakages, special care has to be taken in the mapping of the registers to intermediate values of the algorithm. In this work, we describe an empirical study that reveals effects of unintended unmasking of masked intermediate values and thus leaking secret values. The effects are abstracted to the level of the instruction set architecture on a RISC CPU. Furthermore, we discuss the possibility to have the compiler thwart such leakages.

CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

Research and Design of Superscalar Pipeline Processor Based on CPLD Technology

Superscalar pipelining is to improve instruction-level parallelism and advanced technology, and is widely used in the computer's central processor and graphic accelerator. In this paper, we made use of advantage of CPLD devicesinherent flexibility, usability, predictability and so on, to achieve superscalar pipelining, designed and constructed a processor model superscalar pipeline machine based on RISC instruction set. Using EDA technology with top-down design methods, and gave the processor model hardware verification and performance test results, and had explored the use of EDA technology processor design ideas and methods.

Software-Based Self-Testing of Embedded Processors

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

Instruction translation for an experimental S/390 processor

The IBM™ S/390™ architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even contain two levels of microcode.We report on an experimental S/390 processor based on a RISC processor kernel employing superscalar, out of order execution of instructions. S/390 instructions have to be translated into internal sequences of RISC instructions. Actually two closely coupled internal sequences - one for register based execution and one for storage based execution are generated. The translation is a straight-forward mapping in most cases with some flexibility for special instructions.The paper introduces the hardware mechanisms used for mapping S/390 instructions to internal sequences. The facilities, which provide a greater degree of flexibility are discussed. The interactions of the low-level mapping scheme with the microcode levels is examined. Finally we discuss our experiences with this type of implementation of a CISC architecture on a RISC processor kernel.

A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation

As DSP (Digital Signal Processing) applications become more complex, there is also a growing need for new architectures supporting efficient high-level language compilers. We try to synthesize a new DSP processor architecture by adding several DSP processor specific features to a RISC core that has a compiler friendly structure, such as many general-purpose registers and orthogonal instructions. The synthesized digital signal processor supports single-cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping capabilities in addition to ordinary RISC instructions. The compiler for the new architecture is quickly implemented by developing a code-converter that modifies the assembly codes that are generated by the RISC compiler. The performance effects of adding each of these as well as all the combined features are evaluated using seven DSP-kernel benchmarks, a QCELP vocoder, and an MPEG video decoder. The effects of CPU clock frequency change due to the addition of these features are also considered. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

Dynamically Scheduling VLIW Instructions

Very long instruction word (VLIW) machines potentially provide the most direct way to exploit instruction-level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. In addition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or functional units with different latencies. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Preliminary measurements of the DTSVLIW performance, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.

Analysis of Reciprocal and Square Root Reciprocal Instructions in the AMD K6-2 Implementation of 3DNow!

Reciprocal and root reciprocal functions at “half” and IEEE single precision formats are specified in the AMD 3DNow! instruction set. Implementations in the recently released AMD K6-2 microprocessor are analyzed herein by exhaustive computation and timing loops to ascertain the accuracy and monotonicity properties of the output and throughput/latency cycle counts. Periodicities in stepwise function output were observed and employed to construct an underlying bipartite table that can serve as the core of the respective reciprocal function outputs. The recommended RISC instruction macros generated single precision reciprocals and root reciprocals accurate to a unit in the last place. However, the root reciprocal functions failed to satisfy the desirable monotonicity property typically implemented as an industry standard for elementary functions on x86 floating point units. Reasons for the failure are provided and an adjusted table is shown to satisfy the monotonicity standard. Results are summarized in Table 1 and described in the body of this report.

Implementation of automated fine-granularity locking in a persistent programming language

To gain broader acceptance, Persistent Programming Languages (PPL) need a better integration of the transaction paradigm. Much like database systems, computations should all run in the context of a transaction; the transactional properties should be applied to all objects irrespective of their type and lifetime, and they must be enforced automatically via safe and efficient mechanisms. This requires lock managers that can cope with the requirement for automated locking in a PPL. This paper reports our design and implementation of such lock managers and the accompanying machinery that a PPL must incorporate to automate locking. Our innovative ingredients for an efficient lock management recipe are a close collaboration with the memory manager of the PPL and the sharing of lock data structures of equal value between locked objects. Sharing such lock values has numerous benefits: it makes the space consumption of locking negligible and independent of the number of locks, which frees transactions of any restriction on the volume of locks that they can use; it eliminates the need for expensive book-keeping of locks by transactions; and it enables the use of both non-blocking synchronization and memorization techniques for whole locking operations. These features combine to achieve fast lock acquisition for the non-blocking cases (6 RISC instructions), and make releasing locks practically free. The impact of lock management techniques and automated locking strategy on the performance of a PPL are analysed based on measurements of various lock managers integrated into PJama, a JavaTM Virtual Machine (JVM) which provides orthogonal persistence. Copyright © 2000 John Wiley & Sons, Ltd.

An efficiency model for general purpose instruction level parallel architectures in image processing

RISC instruction level parallel systems are today the most commonly used high performance computing platform. On such systems, Image Processing and Pattern Recognition (IPPR) tasks, if not thoroughly optimized to fit each architecture, exhibit a performance level up to one order of magnitude lower than expected. In this paper we identify the sources of such behavior and we model them defining a set of indices to measure their influence. Our model allows planning program optimizations, assessing the results of such optimizations as well as evaluating the efficiency of the CPUs architectural solutions in IPPR tasks. Besides it lends itself to automatic evaluation and visualization. A case study using a combination of a specific computing intensive IPPR task and a RISC workstation is used to demonstrate these capabilities. We analyze the sources of inefficiency of the task, we plan some source level program optimizations, namely data type optimization and loop unrolling, and we assess the impact of these transformations on the task performance. We observe an eight times performance improvement and we analyze the sources of such speed-up. Finally our study allows us to conclude that, in low-intermediate level IPPR tasks, it is more difficult to efficiently exploit superscalarity than pipelining.

Instruction Set Extensions for MPEG-4 Video

This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures

The impact of Mpact 2

Mpact media processors enable powerful, flexible and cost-effective multimedia in a PC. A single chip replaces today's multiboard, multichip solutions for graphics, video, audio, and communications. The architecture combines a high-bandwidth RAMBUS memory, VLIW/SIMD (single instruction, multiple data) processing, standard buses, and software programmability for the cost of a modern graphics chip. Mpact architecture uses a modified VLIW style with two RISC-like instructions per VLIW. The instructions are either executed sequentially or concurrently based on a tag in the VLIW. Classical VLIW suffers from low code density due to unused instruction fields, but the Mpact modified VLIW has the same code density as RISC instructions. Additionally, the SIMD instructions improve code density by increasing the work done by each instruction. An 8 byte word size was chosen to balance vector and scalar performance and also to balance data and instruction bandwidth. A 9 bit byte was chosen to represent color-component differences in one byte and to represent 18 bit color or 18 bit audio samples in two bytes. Hardware-dithered rounding of quantization noise allows most audio to be processed in two byte precision. The maximal multiplier precision of 24/spl times/24 was chosen for audio requirements. The article reviews the first-generation Mpact media processor and then describes the multimedia performance goals and architecture of Chromatic's second-generation media processor architecture. It then presents newer modules of the architecture in more detail.

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-/spl mu/m CMOS four-metal technology on a 9.84/spl times/10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V.

VIS speeds new media processing

UltraSparc's Visual Instruction Set, described here in detail, accelerates some widely used media-processing algorithms by as much as seven times. Today's new media, increasingly sophisticated 3D graphics environments, videoconferencing, MPEG video playback, 3D visualization, image processing, and so on, demand enhancements to conventional RISC instruction sets, which were not originally designed to handle such applications. The Visual Instruction Set (VIS) is a comprehensive set of RISC-style instructions targeted at accelerating this new media processing.

Design of an RSFQ microprocessor

We are discussing a general-purpose microprocessor architecture that is suitable for implementation using the Rapid Single-Flux-Quantum (RSFQ) family of logic-memory circuits. While the microprocessor provides a functionally complete RISC instruction set with 16-bit words, a bit-serial self-timed approach makes it simple enough to be fabricated using the current Josephson junction technology. Our plans are to design, fabricate and test a completely operational prototype of this system. >

Rationalized three instruction machine

The declarative nature of functional programming languages causes many difficulties in their efficient implementation on conventional machines. The problem is much harder when the language has non-strict (lazy) semantics. Abstract machines serve as an intellectual aid in bridging the semantic gap between such languages and the conventional von Neumann architecture. However they become more and more complex with time as efficiency considerations force the instruction set of the machine to grow in size. In this paper we explain the phenomenon in context of the Three Instruction Machine (TIM). We then define a rationalized instruction set for TIM that allows us to view all enhancements to TIM in a uniform way. This instruction set is quite close to RISC instructions and clearly identifies the key operations on closures. Translation of functional programs to our rationalized instruction set opens up scope for various local and global optimizations. We illustrate this by showing how to build control flow graphs and perform optimizations on it. Lazy arguments in functional programs make it hard to predict evaluation order statistically. We define the notion of pseudo-lazy arguments to statically expose the control flow information, wherever possible, for doing better flow analysis.

Imposing an FP Layer on a Risc Machine

In this paper a simple abstract machine for the translation of FP programs is suggested. The machine simply consists of an instruction selection register (ISR), a pipeline control register (PCR) and a large collection of general purpose registers. It is illustrated how the FP structures may directly be mapped on the ISR and executed. Although the main purpose of the abstract machine was to simplify the translation of FP programs, it is shown that the suggested machine may as well be used to extend RISC instruction sets in a proper healthy way. This will have the effect of simplifying the translation of procedural programs written in any other language. The dynamic nature of the FP combining forms makes it possible to tailor any sort of intermediate instruction suitable for the particular application. The machine may either be implemented at the macro-assembler level or at the firmware level using efficient microcode.

A high-level VLSI design for ultra-dense instruction set computer architectures

At present, typical von Neumann architectures lose more and more of their performance to the memory system. The main reason for this behaviour is the slow main memory. Even if caches alleviate this problem, an advanced architecture has to be developed to provide instructions to the execution unit very much faster than current architectures are able to. This paper describes an advanced system architecture based on ultra-dense instruction sets to overcome the increasing gap between processor and memory speed. Entropy measurements show great redundancy in RISC instruction streams, and therefore a coding technique which can get as close as desired to the entropy is required to encode and decode the instruction stream. Encoding has to be done on static code, the code prior to execution, and decoding on dynamic code, the code during execution. A high-level VLSI design to build the system is suggested.