A high-level VLSI design for ultra-dense instruction set computer architectures

Abstract

At present, typical von Neumann architectures lose more and more of their performance to the memory system. The main reason for this behaviour is the slow main memory. Even if caches alleviate this problem, an advanced architecture has to be developed to provide instructions to the execution unit very much faster than current architectures are able to. This paper describes an advanced system architecture based on ultra-dense instruction sets to overcome the increasing gap between processor and memory speed. Entropy measurements show great redundancy in RISC instruction streams, and therefore a coding technique which can get as close as desired to the entropy is required to encode and decode the instruction stream. Encoding has to be done on static code, the code prior to execution, and decoding on dynamic code, the code during execution. A high-level VLSI design to build the system is suggested.