In this study, an approach to implement wide word-length adders is presented by proposing a hybrid 4-bit carry generator. The proposed hybrid carry generator uses a combination of Carry Look-Ahead (CLA) and Ripple Carry (RC) styles. Utilization of RC style in the first 3-bits aims to reduce transistor count along with power consumption. On the other hand, the CLA method is used in the 4th bit to ensure speed. Also, the proposed CLA for the 4th bit uses a novel approach, which uses inverted Propagate (Pi‾) - Generate (Gi‾) circuits rather than using the conventional ones. Performance of the proposed hybrid RC-CLA based 4-bit carry generator is benchmarked against existing designs. Moreover, the designs (proposed and existing) are used to implement a 16-bit adder to check the effect of using the 4-bit unit cells in a wide word length structure. The proposed design outperforms the existing ones in Average Power and Power Delay Product (PDP). As a result, the design can bring drastic performance enhancement in modern low-power battery-operated devices to reduce power consumption.