Reconfigurable Adder Architectures for Low Power Applications

Abstract

The growing design complexity has attracted the designs with Reconfigurable fabrics, where adaptable fabrics are utilized to solve the computational problems. Reconfigurable computing provides the flexibility in arriving at the problem specific architectures which helps in improving the performance due to custom approach. In this paper, a flexible reconfigurable architecture with different adder variants like Ripple Carry, Carry Look-ahead, Carry Select and Carry Bypass adders are implemented to form dynamically reconfigurable Hybrid adder architectures. Such hybrid architectures are utilized for the applications where design constraints are only for low power or high performance or the low area or sometimes a balanced design metrics. The design was modelled using Verilog HDL and synthesized in Synopsys Design Compiler by mapping to TSMC 65nm technology node. Standard ASIC design methodologies are considered to bench mark the results. The proposed architecture enables the designer to perform efficient Design Space Exploration. The design can be made adaptable to any of the reconfigurable processor and a similar improvement can be obtained. The proposed architectures results in 18-54% reduced power consumption when designed with various combinations of reconfigurable adder architectures and also accounted for 14-44% of area reduction.