An effective BIST scheme for arithmetic logic units

Abstract

Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74/spl times/181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area and performance requirements. In this paper, first, we introduce novel C-testable multifunction ALUs built around RC adders and linear-testable multifunction ALUs built around CLA adders and mined CLA/RC adders with respect to CFM. Then, we introduce an effective ALU BIST scheme for all three types of ALUs (RC, CLA, mixed CLA/RC) that hits the target of a unified datapath BIST architecture, since it is compatible to an effective BIST scheme for datapaths. Complete CFM testability is achieved with a reasonable number of deterministic test patterns in all cases. The scheme imposes reasonable area overhead and negligible delay overhead and owing to its inherent high regularity can be easily adopted for automatic BIST synthesis of datapaths.