Trade-offs in designing High-Performance Digital Adder based on Heterogeneous Architecture

Abstract

To design an efficient integrated circuit in terms of Area, Power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper performance analysis of different available adder architectures has been carried out and then we proposed a Heterogeneous architecture, which composed of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder unit in order to demonstrate trade-offs between performance parameters i.e. Area, Power and speed. We consider area optimization under delay constraint, area optimization under power constraint and finally power optimization under delay constraint. All the adders are design using VHDL. To get power, delay and area report, we use XILINX 9.1 i as synthesis tool and Modelsim XE III 6.2g for simulation. FPGA-Spartan III is used for implementation.