Abstract
In this paper low power implementation of parallel prefix adders using two phase adiabatic logic has been investigated. A new structure has been proposed for the main blocks of parallel prefix adder. Three parallel prefix adders including Kogge-Stone, Brent-Kung and Ripple Carry have been considered. The effects of power clock frequency and loading capacitance on the new blocks have also been considered. Simulation results using 180nm technology parameters and trapezoidal waveform show an average of 34% power reduction in the main building blocks of the adder at 200MHz clock frequency. This power reduces to 54% for sine wave power clock waveform. This research suggests adiabatic implementation of parallel prefix adders for low power microprocessor and signal processing applications.
Highlights
In recent years wide use of portable devices, such as cell phones, tablets and GPSs, has demanded for low power electronic circuit
Parallel prefix adders are among the high speed methods that are used for large number of bits and high speed applications [1]
In this paper 2 phase clock pulse (2PASCL) adiabatic circuit has been proposed for parallel prefix adders to reduce power consumption
Summary
In recent years wide use of portable devices, such as cell phones, tablets and GPSs, has demanded for low power electronic circuit. Many techniques have been introduced to decrease power consumption of parallel prefix adders using lower power supply voltage, node capacitance and switching activity factor. These techniques are not very effective in large scale applications. Adiabatic family circuits have offered lower power consumption comparing to standard CMOS logic [3]. In [5] 2N2N2D method has been introduced that uses diodes to implement quasi-adiabatic circuit. DRDAAL uses Dual Rail Domino for higher speed and lower Power Delay Product (PDP) comparing to static CMOS and quasi adiabatic logic. This paper discusses power reduction in parallel prefix adders using 2 phase clock pulse (2PASCL) adiabatic method.
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