High speed digital filter design using register minimization retiming & parallel prefix adders

Abstract

Design of complex filter solutions from the solution space can be handled at different levels in VLSI design process. Thus, finding reasonably good solutions can consume lot of design time and effort. Hence optimization and automation of filter designs can reduce the design time as well as increase the design performance. In this paper, a Design optimization platform is designed such that synthesisable RTL is obtained from input such as Data Flow Graphs(DFGs) for any digital filters. The optimization is performed using Register minimization Retiming. While synthesizing, architectural optimisations like usage parallel prefix adders is done. The input specifications in the current work are taken in the form of Matrices which are derived from DFGs. Retiming using register minimization is a process in which the location of the registers is altered in such a way that the overall clock period reduces, thereby increasing the clock frequency. This happens due to reduction in the critical path which bounds the speed of the design. Due to intelligent placement of registers in the register minimization retiming, the number of registers gets minimized there by minimizing the area. Since all the Digital filters are made of adders, multipliers and delay elements, optimizing these will in turn increase the design performance. Instead of ripple adders, designs make use of parallel prefix adders. It is found that the combinational path delay of the parallel prefix Kogge-Stone Ling adder is much less which can further reduce the clock period and increase the design speed.