Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs

Abstract

This study describes the design of high speed FIR filter using parallel prefix adders and factorized multiplier. The fundamental component in constructing any high speed FIR filter consists of adders, multipliers and delay elements. To meet the constraint of high speed performance and low power consumption parallel prefix adders are more suitable. This study focus the design of new Parallel Prefix Adder (PPA) and new multiplier cell called factorized multiplier with minimal depth algorithm and its functional characteristics is compared with the existing architecture in terms of delay and area. The performance evaluation of the proposed PPA and multiplier are examined for the bit sizes of 8, 16, 32 and 64. The coefficient of the filter is obtained through hamming window using MATLAB program. The proposed FIR filter using new PPA and factorized multiplier has been prototyped on XC3S1600EFG320 in Spartan-3E Platform using Integrated Synthesis Environment (ISE) for 90 nm process. Nearly 14% of slice utilization and 34% of speed improvement has been obtained for FIR using new PPA and factorized multiplier.