Ripple Carry Adder Research Articles

Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

A Full Adder (FA) is the basic building block of many VLSI sub-systems, and generally it falls into the critical path of the system. Several Transmission Gate (TG) and hybrid CMOS FA designs have been proposed in literature to achieve low Power Delay Product (PDP). But, their performance degrades when used in chain and tree structures, mainly due to poor driving capability. This paper introduces new design approach, a triplet design, to improve performance of TG and hybrid CMOS FA designs in chain and tree structures without inserting buffers. Two new hybrid CMOS FA designs, which are suitable for triplet design approach are also proposed in this paper. Six different FA designs (TG and hybrid CMOS FAs) are chosen to build 4, 8 and 16 bit Ripple Carry Adders (RCA) and multipliers, and we also studied the improvement in PDP using triplet design approach. Schematics and layouts of RCA and multiplier are designed in Cadence Virtuoso using gpdk045 library, and compared based on PDP.

New Design of a 4-Bit Ripple Carry Adder on a Nano-Scale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a new computing paradigm based on cellular automata with appealing characteristics such as high speed, low power consumption, and high density for realizing quantum computers. On the other hand, an adder is the primary circuit in any digital processor and ripple carry adder is a basic building block of other adders. Therefore, efficient design of this type of adder may lead to the efficient design of the whole system. So, in this paper, a new design of ripple carry adder is proposed to decrease the number of cells and area as possible. Simulation results using QCA Designer verifies the correctness of the proposed circuit and validates its efficiency in terms of a number of cells and area.

Implementation of FFT Architecture using Various Adders

In 1965 a technique called Fast Fourier Transform (FFT) was invented to find the Fourier Transform. This paper compares three architectures, the basic architecture/ non-reduced architecture of FFT, decomposed FFT architecture without retiming and decomposed FFT architecture with retiming. In each case, the adder used will be Ripple Carry Adder (RCA) and Carry Save Adder (CSA). A fast Fourier transform (FFT) calculates the discrete Fourier transform (DFT) or the inverse (IDFT) of a sequence. Fourier analysis transforms a signal from time to frequency domain or vice versa. One of the most burgeoning use of FFT is in Orthogonal Frequency Division Multiplex (OFDM) used by most cell phones, followed by the use in image processing. The synthesis has been carried out on Xilinx ISE Design Suite 14.7. There is a decrease in delay of 0.824% in Ripple Carry Adder and 6.869% in Carry Save Adder, further the reduced architecture for both the RCA and CSA architectures shows significant area optimization (approximately 20%) from the non-reduced counterparts of the FFT implementation.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

Delay Efficient Vedic Multiplier for DSP

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

HDL Implementation of Five Moduli Residue Number System

The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n-1, 2n, 2n+1, 2n+1-1, and 2n-1-1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.

Design of a High Speed and Area Efficient Novel Adder for AES Applications

In the design of VLSI circuits, there is huge power consumption because of circuit complexity. It is known that the demand for portable equipment is rapidly increasing now a days. Recently power efficient circuit designs have been concentrated. In complex arithmetic circuits adder is the most important building block. These are widely used in some other applications also like Central Processing Units, Arithmetic Logic Units and floating-point units. In case of cache memory access and in digital signal processing, these are used for address generation. Adders are most significant in control systems also. The speed of a processor and system accuracy is based on the performance of this adder. Regularly, Ripple Carry Adder is elected for two N-bit numbers adder due to fast design time of these RCAs among various other types of adders. Even though if RCA has fast design time, but it is limited in time because of that each full adder must wait for the carry bits of previous full adder blocks. A carry tree adder is proposed in this paper which is efficiently implemented technique at gate level for decreasing the delay and decreasing the memory usage.

Optimization of the area efficiency and robustness of a QCA-based reversible full adder

Recently, quantum dot cellular automata (QCAs) have evolved as the most promising candidate to overcome the fundamental nanoscale limitations of present complementary metal–oxide–semiconductor (CMOS) technology. Owing to their quasiadiabatic switching, QCAs have huge potential for the design of THz-frequency logic circuits and ultralow-power digital circuits with extremely high device density. The aim of the work presented herein is to maximize the benefits of a QCA-based circuit design by deploying reversible computing logic. A highly efficient reversible QCA-based full adder is proposed by using a three-input and five-input majority gate architecture. The proposed design demonstrates significant improvements in circuit complexity, area efficiency, and quantum cost while retaining performance in terms of latency and area usage. Coplanar crossovers are properly realized using 180° clock zones. The performance of the proposed design surpasses that of recent literature designs, with a 25% reduction in the circuit complexity, a 28% saving in the total area, a 24.57% decrease in the cell area, and an approximately 1/4 reduction in the quantum cost. To verify the feasibility of the proposed design, its thermal robustness is analyzed and hazard analysis is also performed. The proposed full adder is further employed to realize reversible ripple-carry adders (RCAs) of variable size. The proposed RCAs also show significant improvements in terms of the mentioned performance parameters.

Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit

DOI: 10.26650/electrica.2019.18052 Arithmetic Logic Unit (ALU) is the essential part of the Central Processing Unit (CPU) core which performs arithmetical operations such as addition, subtraction, division, multiplication etc., logical operations such as and, or, xor etc. and shift-rotate operations. The CPU performance is directly related to the performance of ALU. In this study, the 64-bit ALU has been designed by using the Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Altera Field Programmable Gate Array (FPGA) families, synthesized and simulated with the help of Altera Quartus II (Intel, Santa Clara, CA, USA) v13.0sp1 and Modelsim-Altera v10.1d (Intel, Santa Clara, CA, USA) software. Many different studies are given about ALU Design and Implementation with the use of FPGA architecture and VHDL language. The difference of this study from recent studies is that the proposed design allows the processing of the signed numbers. Also, Conditional Sum Adder (COSA) is used in addition operation instead of Carry Ripple Adder (CRA) or Carry Look-ahead Adder (CLA) because of its benefit in fast addition and less propagation delay of Carry Chain. Cite this article as : Saglam Bedir N, Kacar F. Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit. Electrica 2019; 10.26650/electrica.2019.18052.

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders

This paper introduces two statistical delay-variability models for certain hardware adder implementations, namely, the ripple-carry adder (RCA) and the borrow-save adder (BSA). The introduced models take into account correlated variation sources. Initially, we derive a first proposed model, namely, Type-I model, in the form of expressions for the computation of the exact probability density functions (pdfs) of maximum output delays for Gaussian and non-Gaussian variation sources. Furthermore, we present closed formulas for the covariances between output delays of the aforementioned adder architectures. The introduced derived covariances are subsequently combined with Clark’s method to derive a second proposed model, Type-II model, which comprises approximations of the maximum delay pdfs for an RCA and a BSA. Simulation results and the derived exact Type-I PDFs are found to perfectly agree, while the proposed Clark-based Type-II models present an error for standard deviation of maximum delay that increases as BSA word length increases. Both the introduced models and the simulations prove that BSAs achieve narrower delay distributions than RCAs, i.e., they significantly reduce delay variance. Consequently, BSAs are proven to be suitable for variation-tolerant applications by providing a timing safety margin, when compared to RCA architectures. The underlying analysis indicates that for the case of BSA and either intra-die delay variations only or both intra- and inter-die delay variations, the Type-II models introduce non-negligible errors, which are as much as 16% of the standard deviation of maximum delay for a 256-digit BSA, as the Type-II Gaussian pdf approximations deviate significantly from the exact Type-I PDFs. However, for all RCA and BSA inter-die only variation cases, both types present satisfactory accuracy due to the Gaussian shape of exact pdfs.

Speed and energy optimized quasi-delay-insensitive block carry lookahead adder.

We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm2 area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

A Low Power - High Speed CNTFETs Based Full Adder Cell With Overflow Detection

The transformation from the development of enabling technology to mass production of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the product as implicit pre-cursors. The Carbon Nanotube Field Effect Transistor (CNFET) is the present day technology. In this manuscript, we have used CNFET as the enabling technology to design a 1-bit Full Adder (1b-FA16) with overflow detection. The proposed 1b-FA16 is designed using 16 transistors. Finally, the proposed 1b-FA16 is further used to design a Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) circuit and RCA with overflow bit detection. Methods and Results: The proposed 1b-FA16 circuit was designed with CNFET technology simulated at 32 nm with a voltage supply of +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM. Comparison of the existing full adder designs with the proposed 1b-FA16 design was done to validate the improvements in terms of power, delay and Power Delay Product (PDP). Table 2, shows the results of comparison for the proposed 1b-FA16 with the existing full adder designs implemented using CNFET for parameters like power, delay and power delay product. Conclusion: It can be concluded that the proposed 1b-FA16 yielded better results as compared to the existing full adder designs implemented using CNFET. The improvement in power, delay and power delay product was approximately 11%, 9% and 24% respectively. Hence, the proposed circuit implemented using CNFET gives a substantial rate of improvements over the existing circuits.

Self-timed, minimum latency circuits for the internet of things

This work presents a design flow for asynchronous, self-timed dual-rail circuits which introduces a timing assumption in the return-to-spacer phase. The design flow enables power proportionality and is demonstrated through the design of a 32-bit ripple-carry adder and a 32-bit comparator for internet of things applications. The designs are synthesized to a 65 nm cell library with state-of-the-art transistor sizing for subthreshold. Simulation results show improved performance and energy per computation across operating conditions compared with single-rail equivalents. The design flow allows extension of the power proportional philosophy to a wider range of circuits.

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation

Approximate addition is a technique to trade off energy consumption and output quality in error-tolerant applications. In prior art, bit truncation has been explored as a lever to dynamically trade off energy and quality. In this brief, an innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to state-of-the-art truncation schemes. This translates into energy reduction at a given quality target. When applied to a ripple-carry adder, the proposed bit truncation approach improves quality by up to 8.5 dB in terms of peak signal-to-noise ratio, compared to traditional bit truncation. As a case study, the proposed approach was applied to a discrete cosine transform engine. In comparison with prior art, the proposed approach reduces energy by 20%, at insignificant delay and silicon area overhead.

A single clock cycle approximate adder with hybrid prediction and error compensation methods

A single clock cycle approximate adder (SCCA) with hybrid prediction and error compensation methods has been proposed, where the computing accuracy and energy efficiency are carefully balanced. Meanwhile, the addition could be performed in one clock cycle, which decreases the critical path delay and simplify the configuration when applied to a system. Additionally, the proposed adder is able to prevent larger error output in accumulation computing mode. The new approximate adder is applied into the algorithms of Gaussian filter and Convolutional Neural Network (CNN). The simulation results show that the proposed approximate adder achieves 2.8X speedup and 59.9% Power-Delay-Product (PDP) reduction compared with conventional ripple-carry adder (RCA), respectively compared with two outstanding representative approximate adders in [24,28], 19.3% and 2.4% PDP reduction are also achieved with extremely low absolute errors. Our adder shows negligible output quality reduction in image Gaussian filter, where PSNR decreases from 26.74 dB to 26.72 dB; and CNN is also trained successfully using proposed approximate adder with 0.37% and 9.23% accuracy loss in MNIST and CIFAR10 datasets, respectively.

An efficient full adder circuit design in Quantum-dot Cellular Automata technology

Quantum-dot Cellular Automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. QCA technology has been extensively investigated in recent years. However, only limited attention has been paid to QCA decimal arithmetic. In this paper, an efficient full adder is presented. The layout of the proposed circuit uses 30 QCA cells and a 25% improvement over the best previous design. It has significant improvements in comparison to the previous designs in terms of the number of cells, area and cost and has a similar delay to the fastest previous design. In Ripple Carry Adder (RCA) design, they also maintain high performance. And all of the multi-bit RCA also have the lowest overall cost with a reduction of over 50% when compared with the previous RCA design.

Novel single layer fault tolerance RCA construction for QCA technology

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCA Designer tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time.