RF CMOS Technology Research Articles

Design and Analysis of 2 GHz Low Noise Amplifier Layout in 0.13um RF CMOS

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (Cex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS . And also, this work has been implemented in a 0.13um RF CMOS technology process.

Design of a SAW-less, noise-canceling receiver using an LPTV analysis of a general system with an arbitrary number of N-path filters

This paper, first, presents a Linear Periodically Time-Variant (LPTV) analysis of a general system with an arbitrary number of n-path filters, that the results of mathematical derivations are verified through simulation. Then, a noise-canceling receiver is presented with 3 stages of the 8-path filter. In the structure of this receiver, two filters are used for noise-canceling, and the third filter is used as a Miller bandpass filter to increases the selectivity. The proposed circuit is designed with 65 nm RF CMOS technology and the simulation results show > 44 dB gain, 3–4.5 dB NF, and 0 dBm out-of-band IIP3 at the 50 MHz offset, while in 0.3–3 GHz functional frequency, consuming just 15.52mW of power.

Analysis and Design of High Gain-Bandwidth CMOS Distributed Amplifier Utilizing a Cascaded Pseudo Differential Distributed Amplifier

Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9[Formula: see text]dB can be achieved for a bandwidth of 50[Formula: see text]GHz in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. In this amplifier, parameters S[Formula: see text], S[Formula: see text] and S[Formula: see text] are [Formula: see text]12, [Formula: see text]10 and [Formula: see text]18 dB, respectively; noise figure is 4.3–5.8[Formula: see text]dB, and [Formula: see text] is +4[Formula: see text]dBm. This amplifier consumes 220[Formula: see text]mW power and has a chip area of 0.58[Formula: see text]mm2.

An inductor-less CMOS broadband balun gm-boosting LNA exploiting noise cancellation techniques

This paper presents a 100 MHz to 6 GHz broadband inductor-less single-to-differential balun gm-boosting low-noise amplifier (LNA) for multi-standard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feed-forward thermal noise cancellation technique has been exploited in the design of the inverting amplifier for transconductance enhancement. Moreover, the balanced balun operation transforms the thermal noise of the common-gate transistor into a common-mode signal, and cancels it at the LNA’s differential outputs. The proposed design has been fabricated in a standard 0.18-um RF CMOS technology and occupies a die area of 0.04 mm2. Measurement results have shown that it has achieved a good performance over the whole operation frequency range of interest (100 MHz to 6 GHz) with a gain of 15.5 dB, IIP3 of 1.5 dBm, minimum NF of 3.0 dB and current dissipation of 8 mA at 1.8 V supply voltage.

Analytical phase noise study of a back-gate coupled colpitts quadrature VCO

This paper presents a detailed study of phase noise of an LC Quadrature Voltage-Controlled Oscillator (QVCO). This QVCO is made of coupling two identical cross-connected Colpitts oscillators as core oscillators. MOSFETs are used as varactors, the substrates of which are used for coupling the two core Colpitts oscillators. Phase noise improvement resulted from substrate coupling is not only due to elimination of noise sources (as no extra passive or active coupling devices are used) but also due to lower effective thermal noise of the substrates. To verify this, a rigorous phase noise analysis of the circuit using the Linear Time Variant (LTV) model is performed for the 1/f2 region. It indicates that the improvement is not only due to lower thermal noise of the substrate, but also a better noise modulating factor (NMF). The proposed QVCO was designed and simulated in a 0.18 ​μm RF-CMOS Technology at frequency of 5.35 ​GHz with a power consumption of 8 ​mW, tuning range of 18% and phase noise of −142.8 ​dBc/Hz at 5 ​MHz frequency offset. The presented analysis indicates a phase noise of −143 ​dBc/Hz at an offset of 5 ​MHz, which shows a good agreement with the simulation. The difference between the simulated and calculated phase noise at high frequency offsets is less than 0.2 ​dB.

Design of a Voltage-Controlled Oscillator for Ka-Band Applications

ABSTRACTA varactor-less cross-coupled voltage-controlled oscillator based on triple frequency is presented in this paper, which is optimized for a low phase noise and low power at the high frequency. The VCO consists a voltage to current, a triple frequency, and a mixer with band-pass filter. The varactor-less VCO adjusts the frequency with the current and voltage of transconductance cell. A network RF–CF–RF is applied to filter out the noise of current source at 2. The proposed circuit was simulated in a 0.18 µm CMOS RF technology with a 1.5 V supply voltage. The designed VCO demonstrates an oscillation frequency range from 11.59 to 13.96 GHz with the triple frequency from 35.8 to 40.3 GHz. The simulated VCO presents a phase noise of −110.1 dBc/Hz at 1 MHz offset from a 40.3 GHz carrier frequency. The total figure of merit (FOMT) is −193.113 and −190.83 dBc/Hz with a DC power of 11.32 and 19.56 mW for VCO and total structure, respectively. The layout of the VCO occupies an area of 695.10 µm 627.80 µm.

Bandwidth‐switchable cellular CMOS RF receiver front‐end for intra‐band carrier aggregation

AbstractA bandwidth‐switchable cellular complementary metal‐oxide‐semiconductor radio frequency receiver front‐end design employing a current‐reusing technique is presented in a 65‐nm RF CMOS technology. The proposed single‐ended receiver front‐end can fully support both narrowband and wideband multiple‐channel RF signals for up to three intraband carrier aggregations with high performance and low direct current consumption. To achieve different bandwidth‐handling capability, a narrowband‐ and a wideband‐switchable low noise amplifier is provided to realize appropriate matching conditions and transconductance, while maintaining high performance in multiple component carrier (CC) modes. The design operates at frequency bands of 700‐2700 MHz with 1.2 V. The design achieves conversion gains of more than 40 and 46 dB and noise figures (NFs) of less than 4.9 and 3.5 dB in wideband and narrowband modes, respectively. NF degradation in multiple CC modes is less than 0.5 dB for both bandwidth conditions.

A 10 Gb/s noise-canceled transimpedance amplifier for optical communication receivers

This study presents a noise-canceled transimpedance amplifier (TIA) for optical receivers. The proposed structure consists of a shunt feedback common source amplifier as an input stage followed by two regulated cascodes (RGC) and finally a differential to the single-ended amplifier at the output stage. By exploiting the noise-canceling technique at the input stage, 31.8% of the total output noise is canceled. In addition, the auxiliary path’s RGC circuit, as it has a low input impedance, is utilized to cancel out the photodiode (PD) large parasitic capacitance at the input stage. The proposed TIA along with post amplifiers, including packaging components, are simulated in TSMC 90 nm RF CMOS technology at the post-layout level. The TIA average input-referred current noise is equal to $$9.5\;{\text{pA}}/\sqrt {\text{Hz}}$$. The PD capacitance is considered as 325 fF for all simulations. The transimpedance gain is equal to 60 dBΩ and the 3-dB bandwidth is equal to 7 GHz. The power consumption of the proposed TIA is 3.6 mW from a 1.2 V supply voltage. The TIA occupies a chip area of 0.036 mm2.

A $${\mathbf{g}}_{{\mathbf{m}}}$$-boosted highly linear fully differential 3–5 GHz UWB LNA employing noise and distortion canceling technique

A novel structure is presented to optimize the noise and linearity performance of a $${\text{g}}_{\text{m}}$$ -boosted common gate (CG) ultra-wide-band low noise amplifier (LNA) by exploiting noise and distortion canceling technique. The $${\text{g}}_{\text{m}}$$ -booster common source amplifier provides a degree of freedom to eliminate the limitation on the noise figure (NF) improvement, at a lower transconductance for the CG transistor. The applied noise and distortion canceling technique to the $${\text{g}}_{\text{m}}$$ -boosted topology is used to minimize the dominant noise contribution and the second and third order non-linearity coefficients of the first stage components. The proposed LNA is configured in a differential topology to compensate the $$IIP_{2}$$ of the structure. The Forward body bias technique is utilized for operating the LNA at a lower supply voltage and power consumption. The post-layout simulation results of the LNA, including bonding and electrostatic discharge circuits, with 90 nm TSMC RF CMOS technology show a power gain of 14.5 ± 05 dB, flat NF of 2.2 ± 0.1 dB, and $$S_{11}$$ less than − 9.5 dB for 3–5 GHz frequency at a power consumption of 13.8 mW from 0.7 V supply voltage. The $$IIP_{3}$$ and $$IIP_{2}$$ measures are obtained as + 5.2 dBm and 55 dBm, respectively.

A novel LNA with noise cancellation in 4–11.5 GHz bandwidth for UWB receivers

In this paper, an ultra wide band-low noise amplifier (UWB-LNA) is presented using two new noise cancellation and bandwidth enhancement techniques. The noise cancellation technique was performed using two additional transistors to a common-gate differential amplifier, while the presented amplifier provides a new concept of series inductors to increase the practical bandwidth. Simulation results demonstrate that the minimum noise figure and S21 are 2.75 dB and 21.3 ± 1 dB, respectively. Meanwhile, the average IIP3 in the entire band is 7.5 dB m and the power consumption is 5.15 mW from a 1.2 V power supply. It should be noted that the circuit was simulated in a 65 nm TSMC RF CMOS technology at a bandwidth of 4–11.5 GHz with cadence spectre tool, and has an occupied area of 731 μm × 1816 μm.

Inductor-less PVT robust gain switching balun LNA for multistandard applications

ABSTRACTAn inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor Cc is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in gm is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.

A high efficiency BPSK receiver for short range wireless network

In this paper, a 910MHz high efficiency BPSK receiver is presented with Colpitts oscillator for short range wireless network. In this research, with injection-lock technique and using Colpitts oscillator, the efficiency of receiver has been improved. And also, behavior of an oscillator under injection of another signal has been investigated. Also, variation of output signal amplitude versus injected signal phase variation, the effect of varying the amplitude of injected signal and quality factor of the oscillator has been investigated. The designed receiver has 0.474 mW dc power and -60 dBm sensitivity. Data rate of receiver is 5 Mbps. The FOM of receiver is 94 pJ/bit. This receiver was designed and simulated in 0.18 μm RFCMOS technology. This proposed receiver can be used in short range wireless network for example, Wireless Body array network and wireless sensor network.

A novel UWB low-noise amplifier design using double capacitor cross-coupled feedback

In this paper, an ultra-wideband (UWB) low noise amplifier (LNA) with improvement in noise figure (NF) and gain flatness using 0.18-um RF CMOS technology is presented. Two cross-coupled capacitors (CCC) and new gain flattening technique in a cascode common-gate structure are used for NF and gain flatness improvement, respectively. In addition, NF calculation of CCC cascode common-gate amplifier is presented considering the noise of cascode stage. The LNA operates from 3.1 GHz up to 10.6 GHz with no change in power consumption compared with conventional one. The proposed LNA achieves average S21 of 21dB and S11 less than −10 dB in the entire bandwidth. Additionally, the minimum NF of 2.38 dB is achieved. Furthermore, the power consumption at 1.8 V supply voltage is 4.34 mW and the core layout size for proposed LNA using CCC with and without including new gain flattening techniques are 881μm×1201μm and 680μm×733μm, respectively.

Design of CMOS Reconfigurable Passive Down-conversion Mixer for LTE MTC Receiver

A reconfigurable passive down-conversion mixer is fabricated in standard 65nm TSMC RF CMOS technology and presented in this paper. Different from traditional mixers, transconductor stage in this design is variable, and the transconductance stage uses a second-order low-pass transimpedance amplifier composed of Tow-Thomas structure to form a current-limited filter with adjustable bandwidth. From 900MHz to 1920MHz, The mixer circuit achieves flexible gains(5/11/19/26dB) and variable IF bandwidth(5/7.5/10MHz) with 4-bit control words, while linearity, noise figure and other indicators will also be adapted to suit the requirements of different communication standards.Under the maximum gain, its noise figure NF is 7.8dB; and under the minimum gain, its IIP3 is about 14.6dBm. It drains a current of 3.4/6.3mA from a 1.2V voltage supply at different gain mode.

A Programmable Frequency Divider with Wide Division Ratio and Input Frequency Range

A programmable frequency divider with wide input frequency and divison ratio range is designed in 65nm TSMC RF CMOS technology and presented in this paper. By using the divider-by-2/3 chain, the division ratio of the whole programmable frequency divider covers from 256 to 510. By simulation in Cadence environment, the results show that the programmable frequency divider works correctly when the input frequency varies from 0.2 GHz to 8.8 GHz.

A High Gain, Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.

A digital receiver signal strength detector for multi-standard low-IF receivers

Abstract. This paper presents a receiver signal strength detector based on a discrete Fourier transform implementation. The energy detection algorithm has been designed and measured using a custom multi-standard transceiver ASIC with a low-IF receiver at 0.5, 1 and 2 MHz IF. The proposed implementation directly processes the single bit ΔΣ modulator data and features a clear channel assessment for arbitrary modulation schemes without energy consuming demodulation. Continuous monitoring of the derivative of the RSSI takes advantage of faster coefficient convergence for higher power levels and reduces computation time. A dynamic range of 65 dB has been achieved in FPGA based measurements with a linearity error of less than 1.2 dB. Furthermore, synthesis results for an on-chip implementation for an 130 nm RF CMOS technology show an overall power consumption of 1.5 mW during calculation.

10 Gb/s inductorless single-stage high-gain transimpedance amplifier for optical communication receiver

In the present paper, by simultaneous use of shunt feedback with regulated Cascode structures, a new transimpedance amplifier was presented, which increases the transimpedance limit. This amplifier is very low-noise due to its pseudo-differential nature and partial noise cancellation. The simultaneous use of these two structures led to a reduction in the components of the circuit, power consumption, noise, and the chip area. Moreover, the circuit’s differential output eliminated the need for a separate stage for the single-ended to differential signal converter. The inductorless TIA was simulated with TSMC 0.18 μm RF CMOS technology, with a 3-dB bandwidth equal to 7.38 GHz, proper for functioning at 10 Gb/s, with a 250 fF capacitor to apply the effect of photodiode capacitance at the input. Besides, the single-stage transimpedance gain of 59.7 dBΩ is yielded. Furthermore, the power consumption from 1.8 V voltage source and input-referred current noise were calculated as 5 mW and 12.2 pA/√Hz, respectively.

Low-power Gm-boosted complementary Colpitts LC-VCO/QVCO

In this work, a new differential topology of Colpitts VCO with an enhanced transconductance is presented. The proposed circuit is consisted of an NMOS and a PMOS differential Colpitts cores configured as complementary, and also an LC resonator. The VCO is designed to oscillate at 5 GHz which consumes 1.11 VA from 1.4 V supply voltage. In addition, a modified version of the proposed VCO is designed for lower power applications. This circuit employs new positive feedbacks to enhance the VCO’s transconductance and reduce the supply voltage. The modified VCO operates with 1.1 V power supply while dissipating 1 mW. To investigate the performance of the proposed circuits, the transconductance of them are theoretically analyzed. Also, two new quadrature VCOs (QVCOs) are presented which are realized by two identical latter proposed Colpitts VCOs. A linear analysis is presented to confirm that the first oscillator can generate outputs with 90° phase differences. The proposed circuits are designed in 0.18-μm RF-CMOS technology. Finally, prototype circuits of the proposed VCOs are fabricated to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillators.

A Novel CMOS CCCII with Wide Tunable Rx and Its Application

This paper introduces a novel CMOS second-generation current-controlled current conveyor (CCCII) that has a wide tunable intrinsic resistance ([Formula: see text]. The designed structure is achieved by the combination of one ordinary CCCII, one cross-coupled OTA and one active resistor. An inverse relationship between the intrinsic resistance and external bias current is created for the first time in CMOS CCCII design, which results in wide tuning range of [Formula: see text]. Performance of the proposed circuit is discussed by detailed analysis. The CMOS CCCII is simulated in TSMC 0.18[Formula: see text][Formula: see text]m RF CMOS technology. The simulation results confirm that the proposed CMOS CCCII achieves a wide tunable [Formula: see text] (from 197.4[Formula: see text][Formula: see text] to 27.23[Formula: see text]k[Formula: see text]) while maintaining favorable performance in bandwidth, transfer gain and linear range. In addition, a new reconfigurable structure, which can function as a universal filter or a quadrature oscillator via controlling an enabled switch, is given as an application example to validate the feasibility of the proposed CMOS CCCII.