Abstract
Abstract. This paper presents a receiver signal strength detector based on a discrete Fourier transform implementation. The energy detection algorithm has been designed and measured using a custom multi-standard transceiver ASIC with a low-IF receiver at 0.5, 1 and 2 MHz IF. The proposed implementation directly processes the single bit ΔΣ modulator data and features a clear channel assessment for arbitrary modulation schemes without energy consuming demodulation. Continuous monitoring of the derivative of the RSSI takes advantage of faster coefficient convergence for higher power levels and reduces computation time. A dynamic range of 65 dB has been achieved in FPGA based measurements with a linearity error of less than 1.2 dB. Furthermore, synthesis results for an on-chip implementation for an 130 nm RF CMOS technology show an overall power consumption of 1.5 mW during calculation.
Highlights
Short range wireless systems with low power consumption are increasingly used for communication of sensor networks
A high language description of the hardware was used for the simulations, ensuring early verification of the algorithms functionality
A receiver signal strength detection algorithm based on a discrete Fourier transform algorithm has been presented
Summary
Short range wireless systems with low power consumption are increasingly used for communication of sensor networks. With the increased unlicensed use of these bands by various standards, listen before talk functionality is getting more important to ensure a reliable communication These Clear Channel Assessments (CCA) can be run based on the energy detected in a channel. One method to determine the receiver signal strength indicator (RSSI) value with a high resolution can be found in the digital AGC loop of the digital baseband (BB) filters. These BB filters have a comparatively high current consumption during operation and the digital AGC has a build in hysteresis. Saalfeld et al.: A digital receiver signal strength detector for low-IF receivers
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